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YangZhen
Level 1
Level 1
5 sign-ins First reply posted First question asked

Hello Sir or Madam

We met a strange issue using IC 1EDI3021 and 1EDI3023. We setup driver board together with power module (FS820). When we power on the IC, everything is fine (Power is ok, EN=1, RDY=1, FLT=1) and give 2 pulse to PWM input (give pulse1 3us, wait for 3us and give second pulse 10us). Then strange thing happen. RDY is set to 0 and IC report gate monitor error (DATA duty cycle 1.93). After checked, it seems that during the first pulse, the gate signal does not reach gate monitor threshold (VGATEVCCH). So the error count is still running no matter the first pulse turned off and second pulse turned on. And I checked spec of 1EDI2002 and it clearly defined that after pulse turn on and turn off, the timer would be cleared and recount again. So I want to know what’s the logic of 1EDI30xx for the gate monitoring strategy?

And I do another test is that I keep pulse1 as 3us, wait for 3us but set pulse2 from 50ns to 1us. And I found that if I set pulse2 below 90ns, then no gate monitor error would occur. But if pulse2 exceed 90ns, then gate monitor error always happen. What’s wrong with the IC?

Could you repeat this error at your side?

I am looking forward to your input.

Regards,

Yang Zhen

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1 Solution
Rachel_G
Moderator
Moderator
Moderator
50 likes received 250 solutions authored 250 replies posted

Hi ,

Welcome to Infineon Developer Community,

Functional description gate monitoring of 1EDI3023AS as following: 

The device monitors in the time frame of tGMBT (dynamic or static) the gate signal VGATE at pin CLAMP/GATE
to ensure the signal VTOUT reaches the threshold value of VGATE properly. If monitoring conditions are violated,
the device issues a safe turn-off (if TOUT = high (VCC2) in less than tGM-DaR and changes to Error_Mode in less
than tRDY_GM.

For the tGM-DaR(Gate monitoring detection and reaction time) and tRDY_GM(Gate monitoring detection and notification time),you can refer to the table as below.

Rachel_Gao_0-1662688422199.png

You can also refer to the more details of Gate monitoring in the page29 of 1EDI3023AS datasheet.  

https://www.infineon.com/dgdl/Infineon-1EDI3023AS-DataSheet-v01_10-EN.pdf?fileId=5546d4627956d53f017...

If you have further questions, please contact me.

Best regards,

Rachel

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3 Replies
Rachel_G
Moderator
Moderator
Moderator
50 likes received 250 solutions authored 250 replies posted

Hi ,

Welcome to Infineon Developer Community,

Functional description gate monitoring of 1EDI3023AS as following: 

The device monitors in the time frame of tGMBT (dynamic or static) the gate signal VGATE at pin CLAMP/GATE
to ensure the signal VTOUT reaches the threshold value of VGATE properly. If monitoring conditions are violated,
the device issues a safe turn-off (if TOUT = high (VCC2) in less than tGM-DaR and changes to Error_Mode in less
than tRDY_GM.

For the tGM-DaR(Gate monitoring detection and reaction time) and tRDY_GM(Gate monitoring detection and notification time),you can refer to the table as below.

Rachel_Gao_0-1662688422199.png

You can also refer to the more details of Gate monitoring in the page29 of 1EDI3023AS datasheet.  

https://www.infineon.com/dgdl/Infineon-1EDI3023AS-DataSheet-v01_10-EN.pdf?fileId=5546d4627956d53f017...

If you have further questions, please contact me.

Best regards,

Rachel

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Hi Rachel

Thanks for your input. Pls see our thinking as below. 我们认为1EDI3023 IC在第一个脉冲信号关掉之后没有停止计时,第一个脉冲关断+第二个脉冲上升都不会造成计时器变化。但是1EDI2002规格书就明确规定在信号关断和打开的时候计时器会清零。我们认为这点跟1EDI2002比较,算是1EDI3023的设计bug。请你检查。  

YangZhen_0-1662690768020.png

 

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Rachel_G
Moderator
Moderator
Moderator
50 likes received 250 solutions authored 250 replies posted

Hi ,

每款产品都有各自的应用范围,您可以提出您的设计需求方便我们为您推荐更合适的产品型号。感谢您的理解,后续有任何问题,欢迎随时来到英飞凌社区一起交流讨论。

Best regards,

Rachel

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