Gate Driver ICs Forum Discussions

[ciji_4336356]

This thread is a collection of gate driver IC related questions.

[ciji_4336356]

Target: Optimization of system performance
Better integrated protection of power transistor and application:

• Short circuit protection
  
• Safe shut down after failure
  
• Isolated outputs
  
• 
  

Save PCB space:

• Up to 50% PCB area reduction compared to discrete Optocoupler & Transformer based solutions
  
• Easier to design in (integrated functionality)
  
• Less discrete parts required
  
• Low power consumption
  

[ciji_4336356]

• Functional isolation (1ED020I12-F2, 2ED020I12-F2, 1ED Compact 😞 +/- 1200 V
  
• Basic isolation (1ED020I12-B2/-BT): UL 1577, V_ISO = 3750 V(rms) for 1 minute; VDE 0884-10, V_IORM = 1420 V
  
• Reinforced isolation (1EDS20I12SV): UL 1577, V_ISO = 5000 V(rms) for 1 min; VDE 0884-10, V_IORM = 1420 V, V_IOTM = 8000 V
  

[ciji_4336356]

Only the Isolation classification is different, 1ED020I12-F2 has functional isolation and 1ED020I12-B2 has basic isolation. Pin configuration and application function are the same.

[ciji_4336356]

1700 V EiceDRIVER™ driver IC is not available at the moment.
1700 V EiceDRIVER™ Boards are available (2ED300C17-S / 2ED300C17-ST).

[ciji_4336356]

The Two-Level Turn-Off introduces a second turn off voltage level at the driver output in between ON- and OFF level. This additional level ensures lower VCE overshoots at turn off by reducing gate emitter voltage of the IGBT at short circuits or over current events.

[ciji_4336356]

Based on the current product (1ED020I12-BT), this Two-Level Turn-Off is always on, meaning on each switching cycle (no matter normal operation or DESAT). It gives overvoltage protection for the power device during each switching cycle (include normal case, over current case and short circuit case).

[ciji_4336356]

No. This function is always enabled and no external pin can be used to disable it.

[ciji_4336356]

When the Two-Level Turn-Off signal finishes, there is a delay time to cut off the output, so the same delay time must be shifted to keep the same on-time.

[ciji_4336356]

Soft turn-off is done by RC discharging circuit to reduce IGBT gate voltage smoothly. It is mainly used to control the IGBT turn-off speed during short circuit (DESAT) condition, so as to not abruptly shut off the IGBT short circuit current ->Avoid high di/dt, otherwise this high di/dt will induce overvoltage at IGBT. Once the overvoltage is larger than the blocking capability of IGBT, it will be damaged.
Two-Level Turn-Off is an alternative method compared to the soft turn-off. The difference is that the soft turn-off timing is not controllable and predictable since it depends on the load (so to say, you do not know when it will be really finished), so it is hard to make the control from μC side.
The timing of Two-Level Turn-Off is controllable via the external capacitor CTLSET, so the user definitely knows how long it will take for the Two-Level Turn-Off, so it is easier for the customer to define the control program.

[ciji_4336356]

The internal detection level is 9 V, but the triggering level can be set to a lower voltage by increasing the series resistor since we have an integrated current source on chip for DESAT function.

[ciji_4336356]

• No performance degradation or aging over life time
  
• Higher temperature range Tjmax=150°C
  
• Low propagation delay enables faster switching capability
  
• Low range of temperature drift
  

[ciji_4336356]

The Active Miller Clamp function is fully integrated into our 1ED family driver IC. There is a dedicated clamping pin named “CLAMP”, the gate of the power device just needs to be directly connected to this pin without any resistor in between.
The sinking capability for this Active Miller Clamp is 2 A. In case an external booster is needed at driver IC output stage to drive heavy load (>2 A), a parallel sinking path for the Active Miller Clamp needs to be added to guarantee this function.
For the more detailed information, please refer to the application note Application Note 1ED family: Technical description from Infineon website.

[ciji_4336356]

Using the coreless transformer technology, there is no aging issue, so it can support PV inverters and last for more than 25 years.
Lower conduction loss due to Rail-to-Rail output
Reduce PCB sizes by integrating features and external components.

[ciji_4336356]

• Direct drive up to 75 A IGBT (100°C, <15 kHz)
  
• Indirect drive up to 1400 A IGBT with push-pull circuit
  

[ciji_4336356]

In the application, the calculated max. output current from the driver IC should be smaller than the max. spec value according to datasheet (e.g. 2.4A for 1ED-F2).

[ciji_4336356]

The base current should be lower than max. spec of driver IC, but higher than Iout/Hfe. Iout/Hfe < Ibase < IdriverIC_max

[ciji_4336356]

This value defines when the driver will be turned off when the output chip supply voltage (VCC2) decreases.

[ciji_4336356]

RDY pin will report UVLO status.

[ciji_4336356]

For coreless transformer technology based driver IC (1ED-F2/FT/B2/B2 and 1ED-Compact), the output is level (input signal) related, which means after UVLO recovery (e.g. VCC come back to 15V), the output will turn on with next refresh signal when the input signal is high.
For level shifter technology based driver IC (2EDL, 6EDL), the low side output is also level related, but the high side output is edge related, which means the high side will turn on with the next turn on signal (which means a rising or falling edge transition) from input.

[ciji_4336356]

RST pin function equals Enable. (The IGBT is off if /RST = low).

[ciji_4336356]

Adjustment can be done by value of the DESAT resistor. The constant current source inside 1ED forces a voltage drop over the DESAT resistor, the DESAT diode and the power device itself, so that the DESAT triggers at the remaining voltage of V_MOSFET = V_DESAT – V_Ristor – V_Diode.

[ciji_4336356]

The pin DESAT is not allowed to be forced (even by the junction capacitance of the DESAT diode) below GND2 in any case by more than -0.3V. The only way to achieve this is to use a small signal schottky diode (e.g. Infineon BAT165) between pin DESAT and pin GND. A normal silicon diode is not (!) sufficient.

[ciji_4336356]

Yes, 10 μF CBS is fine. We recommend not designing more than 100 μF for a bootstrap capacitor.

[ciji_4336356]

CBS=1.2*(IQBS*tP + QG)/△VBS
IQBS: the quiescent current of the high-side section;
tP: the switching period;
QG: the total gate charge;
△VBS: the voltage drop at the bootstrap capacitor within a switching period;
Factor 1.2: An additional margin of 20% is added for the case of tolerances for the bootstrap capacitor.

[ciji_4336356]

The pull-up resistor at terminal /FLT should be in the range of a few kΩ (e.g. 4.7 kΩ).

[ciji_4336356]

For the optimum operation, it is necessary to check the transition time of the driven IGBT: the turn-on delay td(on), the rise time tr, the turn-off delay time td(off) and the fall time tf. Also the deadtime which is programmed from the control side should be larger than this value. If the control side does not offer any deadtime, the 6ED003L06-F2 generates a fixed deadtime between the individual IGBT of each half bridge as a safety feature, typically DT = 380 ns. Normally a deadtime of 1 μs to 1.5 μs is sufficient for most applications.

[ciji_4336356]

For this we supply the Psi-Value of Junction to Top which during design and evaluation can be used to calculate a junction temperature. Please refer to application note “Obtaining information about junction temperature by using the thermal coefficient".

[ciji_4336356]

True, and this was never intended, since the driver does not know which voltage levels a customer uses. Btw, if a power supply fails it will most likely affect both positive and negative supply therefore it does not really matter where the UVLO becomes active. Also, there is no feedback to the controller so the application has to monitor the voltage on its own if required.

[ciji_4336356]

Two solutions:
1) use the IGBT version;
2) place an RC-filter on the input.

[User16918]

Hello, I use IRS2186.
Can someone tell me where can get the design guide or the demo schematic for IRS2186?
PWM = 15KHz @ Three Phase Inverter 311VDC 50A
I found that the high low sdie IGBT module(FP75R06KE3) would be short sometime.

[Srivatsa]

Hi Cody,

General design guides are available at [URL="https://www.infineon.com/dgdl/Infineon-HV_Floating_MOS_Gate_Drivers_AN978-AN-v01_00-EN.pdf?file...

and

http://www.infineon.com/dgdl/Infineon-HV_Floating_MOS_Gate_Drivers_AN978-AN-v01_00-EN.pdf?fileId=554...


Kindly review the application note http://www.infineon.com/dgdl/Infineon-AN2006_01_Driving_IGBTs_with_unipolar_gate_voltage-AN-v1.0-en....

Here there are ways to avoid IGBT return-on which can be causing the short.

Best regards,

Srivatsa

[User22602 · Accepted solution]

Design rule for the pull-up resistor at terminal /FLT
The pull-up resistor at terminal /FLT should be in the range of a few kΩ (e.g. 4.7 kΩ).

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