Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Translation_Bot
Community Manager
Community Manager
Community Manager

Does the IC below have a function to automatically turn off the FET when it is in a reverse-connected state?
AUIR3242S
AUIR3241S

One of my customer is serching diode IC. And I found Q-diode function in these ICs.

0 Likes
1 Solution
Tengfei_O
Moderator
Moderator
Moderator
50 replies posted 25 replies posted 50 sign-ins

Dear NXTY_takeichi,

Thanks for getting back to me quickly and sharing additional information.

Based on your previous message, I understand that the goal is to achieve perfect behaviors for your design.
I have looked into the "AUIR3242STR" and found that section 8.7 in the datasheet contains valuable information that may help with your design.
Specifically, I noted that the Vout-Vcc voltage will try to remain at 12.5V or more. In case there is a current reserve from the load to the main battery and the Vout-Vcc voltage falls below UV_LO, the gate output will stop until another cycle of the input is sent to reset the latch.

Best regards,
Tengfei

View solution in original post

0 Likes
4 Replies
Translation_Bot
Community Manager
Community Manager
Community Manager

Dear NXTY_takeichi,

 

Thank you for using Developer Community.

Could you provide a more specific description of the conditions and situation, please?

 

Best regards,

Tengfei

0 Likes
NXTY_takeichi
Level 4
Level 4
Distributor - NEXTY (Japan)
10 questions asked First like given 25 sign-ins

Dear  Tengfei san,

Thank you for your reply.


The ideal behavior is as follows.

NXTY_takeichi_1-1697319422021.png

 


When the drain voltage of the external MOS becomes higher than the source voltage, the external MOS is automatically turned off.
When the drain voltage of the external MOS becomes lower than the source voltage, the external MOS is automatically turned on.

 

I think it is difficult  to realize these. Because there is no way to detect the drain voltage of the extermnal MOSFET.

 

Regards,

Hideki Takeichi

0 Likes
Tengfei_O
Moderator
Moderator
Moderator
50 replies posted 25 replies posted 50 sign-ins

Dear NXTY_takeichi,

Thanks for getting back to me quickly and sharing additional information.

Based on your previous message, I understand that the goal is to achieve perfect behaviors for your design.
I have looked into the "AUIR3242STR" and found that section 8.7 in the datasheet contains valuable information that may help with your design.
Specifically, I noted that the Vout-Vcc voltage will try to remain at 12.5V or more. In case there is a current reserve from the load to the main battery and the Vout-Vcc voltage falls below UV_LO, the gate output will stop until another cycle of the input is sent to reset the latch.

Best regards,
Tengfei

0 Likes
Translation_Bot
Community Manager
Community Manager
Community Manager

Dear Tengfei-sama

Thank you for your support. This is NEXTY Takeshi.
Thank you very much for your answer.

Based on the answers we received, we will consider a little more whether the current from the drain to the source of the external MOS can be cut off at the timing required by the customer.

Thank you very much.

We look forward to your continued support.

NEXTY Hideki Takeichi

 

0 Likes