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Hi all,
I think the diode shown in Figure 26 of the data sheet 2ED21824S06J operates so that Vs won't exceed NTSOA.
Is it correct?
Best regards,
MS
Solved! Go to Solution.
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ispn:24322:1:0
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l1:144:1:0
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l2:1244:1:0
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- clamping diode
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Hello MS,
Thank you for posting on Infineon Community.
When switching happens, the potential of the node between the switches changes.
This fast change can generate oscillations, which may drive the Vs point to negative voltages.
To avoid Vs going lower than the COM potential, this diode can be used.
The diode will conduct if Vs goes lower than COM, therefore Vs will get clamped to near COM potential.
Best regards,
Pablo
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Hello MS,
Thank you for posting on Infineon Community.
When switching happens, the potential of the node between the switches changes.
This fast change can generate oscillations, which may drive the Vs point to negative voltages.
To avoid Vs going lower than the COM potential, this diode can be used.
The diode will conduct if Vs goes lower than COM, therefore Vs will get clamped to near COM potential.
Best regards,
Pablo
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Hi,
Thank you for your support.
Without this diode, is there a possibility that the following problems occur?
Best regards,
MS
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Hello MS,
Yes, that is exactly the problem that the clamping diode solves.
Due to the fast potential change, negative voltage spikes can occur, which are shown in the grey square of the image you shared.
Depending on the gate driver, this could damage the device or cause a false turn-on.
Best regards,
Pablo
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Hi,
Thank you for your support.
Please tell me in a little more detail.
You said that the device could be damaged, but I don't know why. Could you please tell me the reason?
Best regards,
MS
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Hello MS,
From the datasheet, page 17 Chapter 5.10:
"Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications.
An indication of the 2ED2182’s robustness can be seen in Figure 21, where the 2ED2182’s Safe Operating Area is shown at VBS=15 V based on repetitive negative VS spikes.
A negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage; vice versa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside the SOA.
In addition, signal propagation to HO could be stopped due to the negative VS spike:
Best regards,
Pablo