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Gate Driver ICs Forum Discussions

KUOWENYUNG
Level 3
50 sign-ins 10 replies posted 5 replies posted
Level 3

Dear IFXer,

We new have following the 1ED020I12 recommended circuit to design desat function for SIC MOSFET. 

but find abnormal waveform need your help, because the issues cause the trigger the fault. And may I know the Vdesat spike root cause is what? how to avoid it? please advise us.

S__6381570.jpg

KUOWENYUNG_0-1658934062229.png

 

CH1 : Vgs_M

CH2 : Vdesat_M

CH3 : Vds_M

CH4 : OUT

KUOWENYUNG_1-1658934705223.png

 

 

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1 Solution
Jingwei
Moderator
Moderator 50 solutions authored 100 sign-ins 50 replies posted
Moderator

Hi Kuo,

Thanks for the added Info.

The reasons of Vdesat spike root is as following:

1. Increasing Cblank due to D112,D113.

2. Bad filter result of RCD (Rdesat, Cblank, Ddesat) group

3. Changes in current. In gate drive loop, the charge current with several amperes have a large effect on the surrounding area. 

The following page would help to improve. And the link of this docu is also attached.

Jingwei_0-1659343790747.png

Best regards,

Steven

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Jingwei
Moderator
Moderator 50 solutions authored 100 sign-ins 50 replies posted
Moderator

Hello,

Welcome use Infineon Community. The platform is open to all and anyone can give their opinion on issues that they feel comfortable with.


Regarding your problem, I have two requests here.

Firstly can you please provide a clear schematic of your design?

Secondly, could you please mark the test points in the schematic diagram, which you use to get the third picture?

Best regards,

Steven

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KUOWENYUNG
Level 3
50 sign-ins 10 replies posted 5 replies posted
Level 3

Dear Steven,

Thank you. I updated as following schematic and point out the test point as figure.

Test condition

Driver Voltage: +15/-3

Vi=180V, Vo=100V

D=0.556,Io=50A

desat circuit.png

 

 

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Jingwei
Moderator
Moderator 50 solutions authored 100 sign-ins 50 replies posted
Moderator

Hi,

Thanks for your feedback,

I noticed some changes have been made in your schematic (see attached picture). Which circuit did you use in testing?

In order to better help you, one more question is could you add some comments on the use of R115, R116, D106? Why use these components, and why put these between OUTH_M and DESAT_M.

Best regards,

Steven

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KUOWENYUNG
Level 3
50 sign-ins 10 replies posted 5 replies posted
Level 3

Dear Steven, 

I noticed some changes have been made in your schematic (see attached picture). Which circuit did you use in testing? 

Kuo: updated power stage circuit as attached

In order to better help you, one more question is could you add some comments on the use of R115, R116, D106? Why use these components, and why put these between OUTH_M and DESAT_M.

Kuo: R115//R116 is limit current use for accelerate C119 charge speed and D106 use for reverse voltage blocking.

 

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Jingwei
Moderator
Moderator 50 solutions authored 100 sign-ins 50 replies posted
Moderator

Hi Kuo,

Thanks for the added Info.

The reasons of Vdesat spike root is as following:

1. Increasing Cblank due to D112,D113.

2. Bad filter result of RCD (Rdesat, Cblank, Ddesat) group

3. Changes in current. In gate drive loop, the charge current with several amperes have a large effect on the surrounding area. 

The following page would help to improve. And the link of this docu is also attached.

Jingwei_0-1659343790747.png

Best regards,

Steven

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