Gate Driver ICs Forum Discussions

[User16101]

Dear Gate Driver team.

We want to use only High side FET on AUIR2181.
So, We design Lin and Lo Pin to GND as a attach file.


Can we design Lin and LO pin to GND?
Because, The PULSE Generator with LV Detect interface High and Low side as Internal BlockDiagram.

Thanks
Best Regards
Gerald

[Emanuel]

Hi Geraldchoi,

Welcome to the forum.

The function block you have marked with red (UV) is the under voltage detection circuit of the IC.
This function block is used to detect a too low supply voltage (Vcc). If the supply voltage is too low, the gate driver might behave unexpected, and will also not provide sufficient voltage to properly drive the load transistor. For more info on the function, please read this application note especially at page 10.

Regarding the connection of Lin and LO to ground.
It is sufficient to connect Lin to GND and leave LO unconnected as it will anyway be pulled internally to ground.

Best regards,
Emanuel

[User16101]

Hi Emanuel

Thank you for your kindly reply
I will use LIN to GND and LO to NC.

Thanks

Best Regards
Gerald

Emanuel wrote:
Hi Geraldchoi,

Welcome to the forum.

The function block you have marked with red (UV) is the under voltage detection circuit of the IC.
This function block is used to detect a too low supply voltage (Vcc). If the supply voltage is too low, the gate driver might behave unexpected, and will also not provide sufficient voltage to properly drive the load transistor. For more info on the function, please read this application note especially at page 10.

Regarding the connection of Lin and LO to ground.
It is sufficient to connect Lin to GND and leave LO unconnected as it will anyway be pulled internally to ground.

Best regards,
Emanuel

[Emanuel · Accepted solution]

Glad to help you and good luck with your design,

Best regards,
Emanuel