Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

Gate Driver ICs Forum Discussions

xavier1111
Level 1
First reply posted First question asked Welcome!
Level 1

Hi community, hi Infineon support,

we are planning to use the AUIR324x IC gate driver for a battery switching architecture with current constraints of

15A continous, 20A for 2mns, 30A for 10s. We have been testing the "AUIR3241S/AUIR3242S - Board Back to Back 12V" with the batteries and it seems to switch correctly between the 2 batteries.

However at this time we have 2 questions :

- technical : attached TEK0000 (GPIO, Load - resistive electronic 150W load - voltage switching from BAT1=13V to BAT2=20V in ~30us) we can see a first intermediate voltage level for 10us then a small peak at 25V before reaching 20V. Could you explain the signal ?

- commercial : we don't see any stock for AUIR324x IC chip and we want to design a PCB around September. What is the expected planning for procurement of this chip ?

Xavier.

 

0 Likes
5 Replies
Vishnu_Nambrath
Moderator
Moderator 25 solutions authored 10 likes received 50 replies posted
Moderator

Hello Xavier, 

Thanks for posting into our community. 

Technical: You have switched from 13V to 20V in 30us and electronic load is also involved. Can you please share the schematics/block diagram for the circuit for better understanding? Where are the signals probed? uC GPIO and source pin of the power MOSFET right?

Commercial: Procurement has to be discussed with your distributors.  
AUIR3241/ AUIR3242 are active and preferred parts.  If you are looking for any other parts, you can check the product status on our product page. 

 

Regards 
Vishnu N

 

 

0 Likes
xavier1111
Level 1
First reply posted First question asked Welcome!
Level 1

Hi Vishnu,

Thanks for your prompt reply. Below my follow-ups


Technical : please find attached a bloc diagram extract where you can understand that BAT1(13V) and BAT2(20V) are connected to each AUIR324x board, GPIO controls for each board come directly from a uC output 3.3V logic, The GPIO are switched on/off in opposite at the same moment (from a clock cycle point of view at the uC 100ns difference between the switch of each GPIO), the load is connected to the PLUG2/5 pins. The load is an electronic 150W resistive load (like this one https://www.diymore.cc/products/150w-ldm-digital-electronic-load-discharge-capacity-tester-usb-voltm...) allowing up to 7-10A max. The signals probes are GPIO signal for one battery and the other signal is the LOAD voltage signal (basically on MH33).

Commercial : I am glad to know this an active and preferred part and I will follow-up with the local distributor in our country.

Regards, Xavier.

0 Likes
xavier1111
Level 1
First reply posted First question asked Welcome!
Level 1

Hi Vishnu,

technical : did you get my last message ?

commercial : I am now in contact with local dealers, they announce 56weeks lead-time for AUIR324x parts - I hope that I could get samples from Infineon or dealers and shorten this LT.

Best, Xavier.

 

 

0 Likes
Vishnu_Nambrath
Moderator
Moderator 25 solutions authored 10 likes received 50 replies posted
Moderator

Hello Xavier, 

Thanks for sharing the block diagram. I understood your connections. 

Can you try using a high wattage resistor load that draws 7A-10A?  I am suspecting the spike near the end of transition in the load voltage is due to electronic load. 

Regarding the flat region at the load voltage, I am trying in the simulation. 
I shall share my findings soon. 

Regards 
Vishnu N

0 Likes
Vishnu_Nambrath
Moderator
Moderator 25 solutions authored 10 likes received 50 replies posted
Moderator

Hello Xavier, 

I would like to update you on the simulation results. 
I could recreate the measurement results on the simulation test bench and the analysis as follows

Test bench

Vishnu_Nambrath_0-1659443075678.png

  • Load 10 Ohm
  • Delay between the GPIO signals = - 100ns (Why it is negative? First GPIO is turned off after 100ns from turn on of second GPIO. This create an overlap in the GPIO signals as well)
  • First battery 12V and second battery 20V

Waveform 

Vishnu_Nambrath_1-1659443406011.png

  • GPIO signals are in the 3rd graph and curser shows the -100ns delay
  • Gate source voltage of both eval board is shown in the second graph and it shows an overlap here as well
  • During this overlapping period, both eval board MOSFETs are on and creating a cross current between 12V battery and 20V battery
  • This cross current is the reason behind the strange load voltage

Solution : Increase the delay between the turn on an off of the eval boards.
The below simulation shows with a positive delay of 2us between the GPIO signal

Vishnu_Nambrath_2-1659444016950.png

  • No cross current 
  • But there is certain period where load is not supplied by any of the batteries. 

Are you okay to have this dip in the load voltage? if not you can have a capacitor parallel to the load which can supply the load current during the transition. 

Max delays involved with the gate driver is also available in the datasheet as shown below. 
This will help you to optimize the delay between the GPIO signals in your application. 

Vishnu_Nambrath_3-1659444372924.png

Vishnu_Nambrath_4-1659444497831.png

Hope it is clear to you. If not please feel free to ask. 

Regards 

Vishnu N

 

 

 

 

 



0 Likes