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Baptiste
Level 1
Level 1
First reply posted First question asked Welcome!

Hello everyone, 

We are developing a motor controller with the part 6EDL7141 in 3 shunts configuration, with FOC control.

We use the current sense amplifiers of the 6EDL and the noise level is really bad - somewhere around 35mVpp. Combined with a gain of 12 and a 1mR shunt (which seems to be quite normal), that gives us a noise of 3A, which is not acceptable for our application. You will see the noise at the amplifier output in the picture attached (measurement is AC, with a noise floor <1mVpp, BW is 200MHz, passive single-ended probe).

All 3 amplifiers show the same noise shape - which seems slightly correlated after switching, probably due to switching noise being higher than the noise floor, but after that switching transient, the 3 amplifiers noise don't seem correlated. 

The noise level is linked to the gain of the amplifier (the more the gain, the higher the noise level), but it is not a strictly linear relation. We are pretty sure that the noise comes from within the chip because shorting the input of the amplifier doesn't change the behavior, nor does cutting the trace at the output. Noise is also present when not switching the MOS (but the amplifier output has to be activated, otherwise the output is clean). The frequencies of the buck and the charge pump don't seem to affect the noise. Because the noise is not correlated between the 3 amplifiers, we believe it is coming from the amplifier itself and not from an external excitation source.

We thought it was coming from our layout, so we tried measuring on the demo board, but we have the same noise on the demo board.

Placing a capacitor at the amplifier output makes it oscillate very cleanly. Placing a 330R resistor at the output to the ground is the only thing that seemed to have reduced the noise significantly (to about 20mVpp instead of 35mVpp with the aforementioned settings).

Additional info about our system: 48V (tried varying that), 6PWM mode, not using built-in hall functions, no faults are declared apart from a buck OCP on startup, we are in 3.3V logic (quite clean), using internal voltage reference of 1/2DVDD, we have tried many output filter options but without much impact. Battery or tabletop supply don't make a difference.

We tried doing an FFT on the noise but without much success. In our design the noise usually seems to go around 1.2MHz, which is also the frequency at which it oscillates when placing a 10nF to GND at the output. 

 

has anyone experienced this?
Is it a known problem of this chip?
Does anyone have hints or ideas for a workaround? (Or any info/idea at all)

 

Thank you for your help, 

Baptiste. 

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11 Replies
Baptiste
Level 1
Level 1
First reply posted First question asked Welcome!

Hello everyone, 

Quick update regarding this issue, it seems that having one of the 3 amplifiers in disabled mode is causing most of the noise. If the three amplifiers are enabled, the noise levels get significantly better, and the gain setting doesn't seem to affect the noise anymore. 

Because the internal auto-zero is constantly disabling one of the amplifiers, the signal is always bad at the output. 

Still, on the 1 shunt demo board if we enable amp A and C, they are shorted to ground so we are not sure whether it is the fact of enabling the other amplifiers that reduces the noise, or simply the fact of drawing a lot of current.

Our actual setup on the 1 shunt demo board is a 180Ohms to GND at the amp output for signal B (A and C outputs are shorted to ground in the design). B output is followed by the standard filter 470R/330pF.
Auto-zero disabled (very important)
All amplifiers enabled (very important)
Charge pump frequency at 195kHz (minor improvement)
Gain set at 4 (minor improvement)
Buck at 500kHz (1M not tested).
Vref internal at 1/2 DVDD (5V system). The lower Vref, the better the noise (minor improvement).

This is the noise we end up with after the filter. 
This is with 2 probes in parallel - we can see that we reached the max accuracy of our measurement setup for now. This is likely a usable signal, it seems that the remaining noise is mostly coming from the supply and especially the charge pump, which is expected. 

4-4.png

 

Any confirmation on Infineon side that there is indeed a noise issue when disabling one of the amplifiers?
Any specific suggestions?

Best regards, 

Baptiste.

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SuhasBobade
Moderator
Moderator
Moderator
100 sign-ins 50 replies posted 25 solutions authored

 Hi Baptiste,

Thanks for your post.

Sorry for the inconvenience caused.

We are trying to simulate the conditions you mentioned in above posts and replicate the results.

Meanwhile you can try disabling auto zero feature. The Auto-Zero feature can be disabled via register bitfield AZ_DIS in register CSAMP_CFG.

Kindly confirm whether you have connected a resistor between CS_GAIN and GND PIN. If yes, let us know the resistor value.

Thank you!

 

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Disable Auto-Zero function seem not work when use internal Vref. I've no idea why.

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I remember that the Auto-Zero and Current sense timing modes (p.62-64) are a bit messy to understand. I am not sure that everything is working 100% as intended regarding the timing modes (or we did not understand everything). We ended up using externally triggered AZ so it doesn't interfere with the sampling, along with the always-on timing mode. That gave us the best performance in every duty cycle scenario.

Also if you don't use the always-on mode, you might just not see the AZ happening on your scope because it will be hidden; and it took us a while to realize that when the AZ occurs, the amp output is not going back to the offset, it is actually "freezing" the value (because I guess sit's the behavior you want when clock gating with external AZ pin).

And by the way I really recommend using some auto-zero if using internal VREF, otherwise the drift will be strong. We found that the internal auto-zero actually works fine on its own. 

Best regards

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Yes i found strong voltage reference drift when disable AZ function. How often do trig externally triggered AZ? just on startup?

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Drift usually becomes significant in a few seconds, which is why the default internal trigger does it faster. 
We trigger at 20k (our sampling rate), just after finishing our sampling. But we never saw sampling interferences when using internal AZ, I remember we just had issues related to the timing mode when going to extreme duty cycle values.

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zxc594
Level 1
Level 1
5 replies posted First reply posted Welcome!

Any update? I've same problem here. I use 3 of shunt ampifier for low side resistor current sense. If mesure voltage across the resistor the noise is seem smaller than output of ampifier noise. It's very strange if I Pull EN_DRV to LOW to disable chargepump the noise is gone . I've measure noise frequency form output ampifier. it doesn't come form mosfet switching noise. it look like EMI form internal Buck converter and chargepump. I will try to add snubber circuit to reduce EMI form discontinuous current form buck converter.

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Hello, 

We managed to reach a noise level of around 10mVpp on the amp output when filtering at around 1MHz.
We did not relate any noise to internal switching (buck / charge pumps don't seem to interfere).
We did not see an improvement if sampling when the charge pumps are disabled (through AZ function).

After doing a bode plot of the amplifiers, we saw they are unstable above 1MHz. If you can afford to filter below 1MHz, you can get noise lower than 10mVpp. To us it seems to be the only drawback of this IC (a  major one though).

If you see noise coming from the charge pumps, try changing their frequency to be sure.
Disabling EN_DRV also disables the amplifiers, and they don't make noise if they are disabled (p.80)

Baptiste_0-1675070035211.png

If your noise is coming from the charge pumps, you can experiment using the AZ clock gating function (p.71) that disables the charge pumps while the AZ pin is held high. In our case, the waveform becomes noise-free, but it is not stable (voltage drifts higher or lower randomly) so it did not bring better results.
Note that, as far as I understood, when clock gating I am not sure that the amp output are still connected to the amps. So that could potentially solve your issues but it wouldn't mean that the noise is actually coming from the charge pumps. 

Regarding the layout, my recommendation would be to be careful about keeping PVDD and DVDD well separated (to avoid crosstalk from the buck inrush current). And be very careful with the traces going from the shunt to the IC.
We did not see any improvement using external VREF.
To identify routing issues, try spotting differences in behavior between the 3 legs, if there are differences, it's probably layout.

Hope that helps, 

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Thank for your reply. It's help me a lot. I just see the AZ clock gating function (p.71) form your reply. But you not see any noise coming from the charge pumps. I will check my layout to avoid crosstalk from the buck inrush current and come for update.

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喜马拉雅之雪
Employee

Hi Bartiste:

Thanks for your comments.

Would you like share your PCB and SCH?

For noise test, two probe test function is not better. This is our favorite:

_0-1675064699585.png

Would you like double check the noise by the tools?

 

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zxc594
Level 1
Level 1
5 replies posted First reply posted Welcome!

I also use this technique to measure noise across shunt resistor and amp output.

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