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Gate Driver ICs Forum Discussions

kagarwal37
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Hi,

I'm using GaN MOSFETs for my project application and I'm looking for a suitable gate driver chip to drive these MOSFETs. The datasheet for the MOSFET I'm using is this: https://epc-co.com/epc/Portals/0/epc/documents/datasheets/epc2055_datasheet.pdf

The overall switching specs for the MOSFET are: Vds = 18V; Continuous Id = 15A; switching frequency = 200kHz; Target rise time = 10 ns 

By inspecting the 2EDF7275K datasheet, it seems like it would be a good option as the UVLO threshold is around 4V, allowing me to drive the MOSFET at 5V. Also, the high source and peak current capability is also looking sufficient to meet my target rise/fall times.

Could you please offer any advice on whether it would be suitable to use 2EDF7275K for driving the MOSFETs I have linked above?

Sincerely,
Kartavya Agarwal.

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1 Solution
Guru_Prasad
Moderator
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Hello @kagarwal37 

Thanks for explaining your requirement clearly 

I went through all possible combinations and circuits most simple and easy solution is 2EDF7275K

The 2EDF7275K can be used for all switches(Q1, Q2, Q3, Q4), and the negative can connection can

also can make you can see the below-mentioned circuit.

Guru_Prasad_0-1649916652113.png

while you are connecting Q1 and Q2 make sure your connections and PWM should be the same for

both switches and size your power supply accordingly.

Please let me know if you need any  help

Thanks

Guru

 

View solution in original post

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Guru_Prasad
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Hello @kagarwal37 

Thanks for posting your question in the Infineon community.

Yes, The 2EDF7275K can be used for : Vds = 18V; Continuous Id = 15A; switching frequency = 200kHz;

since your Target rise time = 10 ns , the 2EDF7275K datasheet mentioned is 12ns so you need make your driver

layout such that it should not cross more than 12ns.

The UVLO is not a problem in your IC but it cannot be ignored so for that you need make less tolerance for your

power supply.

2EDF7275K can  used for your attached datasheet.

Thanks

Guru Prasad

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kagarwal37
Level 2
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Level 2

Hi Guru Prasad,

Thank you very much for the information. Could you please elaborate on what you meant by: "The UVLO is not a problem in your IC but it cannot be ignored so for that you need make less tolerance for your power supply."

I did not understand what you meant by this. Did you mean that since the UVLO is around 4V, I just have to ensure that there is enough margin on my Vdd chip power supply so that it doesn't trigger a lockout? Would 5V be sufficient, since I plan to drive the MOSFET at +5V for turn on?

Also, would you be able to recommend how much negative bias I should apply, considering this is a GaN MOSFET?

Sincerely,
Kartavya Agarwal.

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Guru_Prasad
Moderator
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Hello @kagarwal37 

Since you are planning to drive your GaNFET with 5V, the power supply VDD is +5V and your UVLO is 4V so your

supply voltage should not be less than 4,  to maintain your VDD>4V power supply tolerances should be maintained accordingly.

The Negative voltage should same as maximum threshold in your case it is 2.5V(from your data sheet) so you need

provide -2.5V to fully turned OFF your device.

Thanks 

Guru

 

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kagarwal37
Level 2
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Level 2

Hi @Guru_Prasad,

Thank you very much for that information.

Could you also please clarify how I can use the 2EDF7275K driver to apply a negative voltage to the MOSFET? The chip pin out doesn't have a common ground reference pin per channel which could be connected to the power supply ground. For a low side switch, the main GND pin of the gate driver IC would be connected to the power switch source, which is sitting on the power ground. This obviously clashes with the negative voltage that must be applied.

So my question is how can I adapt the gate driver IC to drive a negative gate voltage for the MOSFET, assuming I have access to -3V power supply rail from an external isolated DC supply?

Also, why is the negative voltage same as the maximum threshold voltage?

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Guru_Prasad
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Hello @kagarwal37 

The 2EDF7275K can able to connect a negative supply.

The below two options I am giving to your application 

Option-1 if your application is automotive use 2ED020I12FA. 2ED020I12FAis having all protection feature. use

external booster for more current capabilities 

Option-2 if your application is industrial grade use 1EDF5673K with basic feature more driving capability. 

The 1EDF5673K is single channel and it specially made for Gan 

can you provide below information about design

1)Application?

2)Topology?

3)expected features in gate drives ?

4)what is your drive current requirement?

Thanks

Guru

 

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kagarwal37
Level 2
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Hi @Guru_Prasad,

Here are some answers to the questions you posed:

1. Application: 300V-12V 150W isolated DC-DC converter

2. Topology: Please see the attachments for the file labelled "Schematic" for the topology. The high level specs are as follows: Input Voltage = 300V, Output Voltage = 12V, Switching frequency = 200kHz, Output Power = 150W. I intend to use GaN as Q3 and Q4 MOSFETs with this datasheet: https://epc-co.com/epc/Portals/0/epc/documents/datasheets/epc2055_datasheet.pdf

3. Gate Drive features: DESAT protection, isolated gate driver, applicable for GaN MOSFETs. I'm not sure if I need active miller clamp, could you please advice on this?

4. Drive Current Requirement: The datasheet for the GaN MOSFET I intend to use shows a total gate charge of approximately 8 nC. As mentioned before, my optimistic rise time target would be around 10-20 ns. Faster than that would be better. I also intend to drive the GaN MOSFETs at +5V, -3V

Moreover, I'm looking for gate driver IC solutions that are relatively low cost and are in-stock to purchase. In addition, I'm also thinking of using GaN MOSFETs for Q1 and Q2 shown in the schematic attached. The datasheet for the GaN MOSFETs I'm thinking of using as Q1 and Q2 is here: https://www.transphormusa.com/en/document/datasheet-tp65h480g4jsg/

Could you please suggest some low cost, in-stock to purchase, GaN gate driver ICs for my application as above for GaN MOSFETs for Q1, Q2, Q3, and Q4?

Sincerely,
Kartavya Agarwal.

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Guru_Prasad
Moderator
Moderator 100 replies posted First question asked 10 likes received
Moderator

Hello @kagarwal37 

Thanks for explaining your requirement clearly 

I went through all possible combinations and circuits most simple and easy solution is 2EDF7275K

The 2EDF7275K can be used for all switches(Q1, Q2, Q3, Q4), and the negative can connection can

also can make you can see the below-mentioned circuit.

Guru_Prasad_0-1649916652113.png

while you are connecting Q1 and Q2 make sure your connections and PWM should be the same for

both switches and size your power supply accordingly.

Please let me know if you need any  help

Thanks

Guru

 

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kagarwal37
Level 2
25 sign-ins 10 replies posted 10 sign-ins
Level 2

Hi @Guru_Prasad,

Thank you very much for the explanation. Would you be able to provide any guides that explain how to make the negative supply connections? Also, how should I size those decoupling capacitors between -3V supply and 0V ground?

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Guru_Prasad
Moderator
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Hello @kagarwal37 

The negative connections can make two way's

1)Take two power supplies +5V and +3V and connect the +3V to opposite sign of your power supply. In your case generate positive +3V  from your power supply and connect to opposite. Please referrer below circuit.

Guru_Prasad_0-1650260326324.png

 

2)Take +8V  and make positive and negative supply from single source. Please refer below circuit. Please size your C1 and C2 based on potential divider rule if switching frequency is fixed. Otherwise better calculate with i=C*(DV/DT). 

 

Guru_Prasad_1-1650260877868.png

Note: Before finalizing part number Please check DC bias characteristic of selected capacitor 

Thanks

Guru

 

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kagarwal37
Level 2
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Level 2

Hi @Guru_Prasad,

My apologies, but I should clarify my question. I am wondering how to connect a -3V rail I have designed already to the 2EDF7275K chip. To better understand your response, I have drawn a schematic to clearly illustrate my concern. Please refer to the schematic drawing in the attachments to this reply.

Just to clarify, the question is as follows: Based on the schematic attached, where do I connect GND1, GND2, GND3, and GND4? Do GND1 and GND2 connect to the node labelled MID, whereas GND3 and GND4 connect to node labelled PWR_GND?

 

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Guru_Prasad
Moderator
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Hello @kagarwal37 

Since you are getting -3V_A w.r.to Gnd2 and -3V_B w.r.to Gnd4 you have to do below connections

1)connect Gnd1, Gnd2, and Mid as a one node

2)similarly Gnd3, Gnd4, and PWR_gnd as a one node 

Thanks

Guru

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kagarwal37
Level 2
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Level 2

Hi @Guru_Prasad ,

Thank you very much. Also, last question, if I want DESAT protection and fault signalling from the gate driver chip as well, is there any way to incorporate that with 2EDF7275/35K?

If not, can you suggest chips that meet my previous requirements but also support DESAT protection and fault signalling?

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Guru_Prasad
Moderator
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Hello @kagarwal37 

Generally, we use DESAT for IGBT and Over Current Protection (OCP) for MOSFETS.

In GaN MOSFETs also you need to use OCP, since  2EDF7275K  is not having OCP, you need

to use external shunt for current measurement and use the comparator for Disabling the

Gate driver.

 The raise time and peak current requirements are not matching In other Infineon ICs.

Kindly use external circuit or SW protection.

Thank you

Guru

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kagarwal37
Level 2
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Level 2

Hi @Guru_Prasad,

Do you know of any reference designs I can use to add this functionality externally?

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Guru_Prasad
Moderator
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Hello @kagarwal37 

HW solution

The external circuit is shown in the below circuit. The differential  Isolation op-amp will measure the voltage across the R3 and the voltage will be amplified and given to the comparator. The comparator will give disable signal to gate driver disable while the current is exceeds beyond the limit hence your over current protection will be performed. The OR gate also used in this circuit to  perform OR operation in the circuit . The OR operation will perform between your uC signals and comparator signals. This circuit is costly solution because it is adding additional HW components to your system. The cheaper solution is SW implementation.

Guru_Prasad_0-1650518066083.png

SW solution

The SW solution will be measure your system current and set the threshold for Over current. Once the measured current reaches above threshold value you can initiate the GD disable signal.

 Thanks

Guru 

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Laneve
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First solution authored First reply posted Welcome!
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