Announcements

The EV market is bigger and better than ever. Join the EV Webinar to find out how you could best utiilize Gate Driver ICs for EVs.

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

Gate Driver ICs Forum Discussions

Joel_H
Level 1
Level 1
First reply posted First question asked Welcome!

Hello,

I made a half bridge test board similar to EVAL_1EDF_G1B_HB_GAN but with 1EDS5663H and IGT60R190D1SATMA1 parts, and added a trimpot in series with the recommended 18k resistor to set tneg, but it doesn't seem to work, I don't even get the theoretical minimum tneg of around 190ns. Could the drivers be the old version which needs a capacitor?

I also get some nasty ringing on the high side gate drive, which component value would you recommend to change?

Thanks,

Joel

 

0 Likes
1 Solution
Xiangrui
Moderator
Moderator
Moderator
50 solutions authored First question asked 50 sign-ins

One more hint: parasitic capacitor has a strong influence on the negative voltage time. So, you can firstly remove the trimpot and test again.

View solution in original post

0 Likes
7 Replies
Xiangrui
Moderator
Moderator
Moderator
50 solutions authored First question asked 50 sign-ins

Hi Jeol,

You can set up TNEG circuit refer to my last answer: https://community.infineon.com/t5/Gate-Driver-ICs/1EDS5663H/td-p/379263 

And a 10.8pF capacitor is not necessary.

BR,

Xiangrui

0 Likes
Xiangrui
Moderator
Moderator
Moderator
50 solutions authored First question asked 50 sign-ins

Hi Jeol,

190ns is not the minimal time for negative voltage, but it is theoretical value for 18k resistance on TNEG. 

I've checked it with the simulation circuit below. As you say, this time interval should be around 190ns. 

TNEG circuit.png

So I suggest you to check your PCB board, especially the exact resistance on TNEG Pin. 

Furthermore, how is your VCC and VDD2?

0 Likes

Hi Xiangrui,

Thanks for your prompt reply, I already checked the exact resistance between pin 6 (TNEG) and the primary ground plane, it is as expected, between 18k and 65k, depending on the setting of my trimpot:

Joel_H_0-1669792236276.png

 

I will check the supplies next Friday, but I can already tell you that I use SIP8 converters, SPBW03G-05 for the primary supply, with the series 470R and 22nF cap, and TEC 2-4819WI for VDD2:

Joel_H_1-1669792642902.pngJoel_H_2-1669792722808.png

 

What is the purpose of R4 in your simulation?

Thanks again

BR

Joel

0 Likes
Xiangrui
Moderator
Moderator
Moderator
50 solutions authored First question asked 50 sign-ins

Hi,

R4 and R17 in your schematic are identical. It is a standard 10 k gate pull-down resistor that helps ensure the gate-source voltage remains at zero even when the gate driver is unpowered.

I don't see any issues in your circuit. So, I think it's better to check the driver IC without any other ICs before it. You can supply VCC with 3.3V and VDD with 9V. Let SLDO and DISABLE floating and give PWM with PWM generator to make sure if 1EDS5663H is in working order (i.e. has 190ns negative voltage time with 18k on TNEG.)

BR,

Xiangrui

0 Likes
Xiangrui
Moderator
Moderator
Moderator
50 solutions authored First question asked 50 sign-ins

One more hint: parasitic capacitor has a strong influence on the negative voltage time. So, you can firstly remove the trimpot and test again.

0 Likes

Hi Xiangrui,

I tried almost everything to no avail, and then I noticed the marking while changing for a new IC:

Joel_H_0-1669978143961.png

Current version marking is supposed to be 1S5663B according to the datasheet.

So I think I got an old version which needs a cap, according to the app note AN_1811_PL52_1811_234307:

"C18 and C28 are for an earlier version of the driver IC and are not required, so are not populated on the PCB."

So, my question is, what is the value of the cap for this earlier version?

Best regards,

Joel

0 Likes
Xiangrui
Moderator
Moderator
Moderator
50 solutions authored First question asked 50 sign-ins

Normally there is no functional difference between A and B. But you can try to add a 10.8pF capacitor to build up a RC network for testing. I simulated that it affects little on the time interval even for the new version.

0 Likes