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Gate Driver ICs Forum Discussions

VaBaSPI
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Hi, I have an issue with the 1EDI60N12AF gate drive used within a bootstrap circuit for the top switch.

Following situation: primary side is supplied by 5V, the output is not supplied until the bottom switch is activated for the first time (=normal bootstrap initial condition).

When the initial condition of the driver side supply is 0V: the gate of the switch is charged slightly&slowly through the gate driver (not due to parasitic capacitors). The gate voltage rises to values around 5...8V, depending on the dV/dt of the boot strapped supply voltage (is round 5...10V/us in my case). The datasheet states: "In case of UVLO an active shut down keeps the output voltage at a low level." Which is not the case, although there is an additional 10k pulldown to source on the gate.

When the initial condition of the driver side supply is ~2.5V (far below UVLO) the above situation is not observed. That voltage can be achieved by some 100uA bias current generated by an high value R across the bottom switch.

However, I'm not sure if that behavior is normal/intended and if the work around is reliable or if there is another way to overcome.

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1211Shukla
Moderator
Moderator 25 sign-ins 5 solutions authored 10 replies posted
Moderator

Hi,

While going through your question, I can understand that you are using 1EDI60N12AF  single channel isolated driver. I am not sure how come you are implementing a bootstrap in there. Is the driver for bottom switch is different than the top switch. Please share the schematic for better understanding.

Regards,

Rishabh S

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VaBaSPI
Level 1
First reply posted First question asked Welcome!
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You understand correctly: there are two single channel gate drivers for each phase. The driver for the top switch is supplied by bootstrapping. I added a simplified schematic with the relevant values and indicating the voltage measurements. The colors of the arrows match the colors of the traces in the measurement. I hope it helps.

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1211Shukla
Moderator
Moderator 25 sign-ins 5 solutions authored 10 replies posted
Moderator

Hi,

Since you want to test UVLO operation of the gate driver 1EDI60N12AF . I would like to recommend you to perform the test as per the Fig.8 in the datasheet. Just make the IN+ signal always high, vary VCC1 & VCC2 in respective order and observe the OUT signal of the gate driver as per data in Table 4 in the datasheet.

1211Shukla_0-1663876186526.png

1211Shukla_1-1663876467026.png

I have also simulated the circuit shared by you with 1EDI60N12AF spice model in ltspice, where UVLO operation is performed perfectly fine. I have attached the result for you.

Do revert back in case of any query

Regards,

Rishabh S

 

 

 

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VaBaSPI
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Hi Rishabh,

Thanks for your effort! Actually I don't want to test the UVLO operation. I simply see that it does not behave like I expected it from reading the data sheet: In+ is 0 in my case, now when VCC2 rises (due to bootstrapping supply), the output starts to increase, although VCC2 is far below UVLO. That's the issue, I expect to stay Out at 0V. I've drawn my situation into the graph of the datasheet:

DatasheetGraph.png

 To my understanding: Out should stay low, but according to my measurements it does not:

InitialCondition0V.png

 The peak Out-voltage depends on the VCC2 rise time (blue). Higher rise time give higher Out-voltage. That issue disappears when VCC does not start from 0 but from 2.5V:

InitialCondition2_5V.png

I've simulated both situations in spice as well, there the problem does not exist.

 Best regards

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1211Shukla
Moderator
Moderator 25 sign-ins 5 solutions authored 10 replies posted
Moderator

Hi,

Let me also know  the exact input conditions in the  circuit block diagram shared by you. When you say that IN+ is 0, whether it is connected to GND(as you drawn) or floating. Please Connect IN+ to GND, IN- to High then observe and share the results in a separate graph. 

Regards,

Rishabh S

 

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VaBaSPI
Level 1
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I didn't take into account, that it is related to the input, as it is driven as shown below:

RelevantSchematic3.png

The top and bottom switch control signals are connected "inverted" to each other, that gives a very basic shoot-through protection. Initial condition is: All In+ and In- are low (and subsequently the gate outputs as well).

Then In+ of the bottom switch goes high and turns the gate on. In the same instance In- of the top switch goes high as well, as you propose. According to the datasheet the gate of the top switch should be held low in any case (In+=In-=low and In+=low, In-=high).

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