Gate Driver ICs Forum Discussions

[Neil]

Hi,

I am trying to simulate the 1EDB9275F driver chip in LTSpice using the PSpice model downloaded from the website.  It seems to work as expected, but there is one issue.

I am suppling VDDI with 12 V and the model is showing a quiescent current of 870 mA. The datasheet indicates that 870 uA would be more reasonable. 

Can you confirm that this is an error in the model and that the chip does not take this much current.

[Abhilash_P]

Hi,

   Thank you for posting on the Infineon community.

The quiescent current value specified in the datasheet is at the following test conditions,
1) VDDI = 3.3 V
2) VDDO = 12 V
3) No switching condition.

In your simulated test condition I can see that the input supply voltage is 12V. Please do verify this. 

The following graph shows the variation of IVDDI with respect to VDDI. ,

From the graph it is clear that at VDDI = 12V, the IVDDI will be around 1mA during no switching condition. 

I hope from the above explanation it is clear that why you are getting a quiescent current of 850mA. 

Regards,
Abhilash P

[Neil]

Hi Abhilash 

I did see that figure in the datasheet, but it is not replicated in the simulation. If I keep the VDDO power supply fixed at 12 V, I don't switch the input and sweep the VDDI supply, the power taken goes from just under 1 mA at 3.3 V supply to over 1 Amp at 14 V. The graph you are showing indicates it should 1000 times less. 

I have tried replicating this with the connections below

This circuit produces the graph shown here

 This is far from the flat line in the datasheet

Yours

Neil

 

[Abhilash_P]

Hi,

   The circuit connection is not accurate. The gate driver IEDB9275F is an isolated gate driver IC. Hence the input power supply ground and the output power supply grounds has to be isolated. It shouldn't be connected directly.  VDDI supply is primarily given from a controller IC. And the VDDO supply is from a bench / bootstrap capacitor supply. 

Hence the currents are getting added up here due to common ground. 

While simulating please use two ground planes, namely SGND and PGND. 

I hope the above explanation is clear. 

Regards,
Abhilash p

[Neil]

Hi Abhilash,

I have simulated this with the ground planes split as suggested, the device is still pulling current as I showed in the earlier graph.

The application I am looking at using this device on will be switching several IGBTs in series. To ensure they all switch at the same time  I want to use the same driver for each stage. The bottom driver will have GNDI and GNDO at the same potential. Are you saying that the actual device will be trying to dissipate 6W if I am suppling 10 V?

[Abhilash_P]

Hi,

   Since it is an isolated IC, GNDO and GNDI should be at different potentials. 

GNDI is referred to microcontroller ground and GNDO is referred to power ground.

Regards,
Abhilash P

[Neil]

As I said in my earlier post, separating the two grounds in the simulation does not affect the current draw on VDDI. It is still over 1 A quiescent current at 14 V.