Hello,
I have a question RE: the RDYC fault clear input function on the EiceDRIVER™ 1ED34x1Mc12M Enhanced gate drivers. I'm working on a design to replace legacy gate drivers used for an inverter IGBT stack in an H Bridge configuration. The trouble is the existing design does not have easy access to a microcontroller output (without a more significant redesign) to perform the RDYC fault clear input function, and instead only uses 1x pin on the existing microcontroller to report a fault (i.e. similar as FLT_N to detect Desat etc.).
The existing driver will latch in an internal fault state and clear internally after ~30uS (if all fault conditions are removed, gate driving has stopped etc. and the error out/error in pins are tied together). And the 1x output to the microcontroller we do have allows all other inverter functions to be stopped during the fault until reset by the user externally.
My question is, is there a recommended way to handle the RDYC fault clear input function in this scenario? I've noted through testing of the evaluation board and analysing the datasheet the RDYC needs a rising edge to reset. And there doesn't appear to be anyway (that I can see) to bypass or disable this need.
Kind regards,
