I am having trouble controlling the MSLS / Chip select signal.I want it to enable at the start of a frame and disable after the last byte is transmitt...
Show More
I am having trouble controlling the MSLS / Chip select signal.
I want it to enable at the start of a frame and disable after the last byte is transmitted.
The SPI001 app is configured to use FIFO.. Great. As long as the FIFO is not empty, the CS signal behaves properly. However, I am in an RTOS environment so occassionally, the service time allows the fifo to empty and CS pulses. This disturbs the slave - it cancels the current command.
I attempted to use the frame control interface..
EnableStartOfFrame( pScb->Handle );
// Send the command..
SendSpiWord( pScb, Cmd );
SendSpiWord( pScb, IDLE0 ); // Put something in the Rx buffer...
. . .
// Wait for all our data to go..
while ( ! SPI001_GetFlagStatus(&(pScb->Handle), SPI001_FIFO_TRANSMIT_FIFO_EMPTY ))
;
//while ( SPI001_GetFlagStatus(pScb->Handle, SPI001_TRANS_SHIFT_IND_FLAG ))
;
EnableEndOfFrame( pScb->Handle );
I enable the frame.. then send..finally wait for FIFO to empty... But that is too late to get the EOF set - the last character is transmitting.... So my sessions ends with CS active. Then the first byte of the next frame has CS pulsed just for that first byte...
Without the test on FIFO_TRANSMIT_FIFO_EMPTY, the CS EOF happens too early.
NOTE: FIFO EMPTY is something I defined to access that bit of TRSB.. It is defined at 64+Bit Number in the register.
The notes in the UM describe CS control, but most do not use FIFO.. The section on FIFO is vague.
What is my best strategy? Options seem:
- Use FIFO. Let it control CS... Just make sure it doesn't empty prematurely. Maybe tx interrupt service routine to extrace from RTOS queue.
- Switch to non-fifo interface, scrapping the app. More work, but precise control.
I looking for general direction suggestions.
Show Less
Nov 21, 2015
