Uart Fifo Timeout Interrupt

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Good old 16550 uart device had a fifo timeout interrupt.

If you use f.e. 16 bytes fifo as a uart receive buffer and set the receive trigger to about 10,
how will you get an interrupt when only one byte arrives ?
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6 Replies
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Hi VTrapp,

If you want to generate an interrupt when one byte/word data has been received, you can use the standard receive interrupt (AIF and RIF flag in PSR register). You can add one interrupt app (e.g. NVIC002) and enable it by connecting signals “Alternative Receive Interrupt” and “Standard Receive Interrupt” to the "Interrupt Node". Pls refer to user's manual (17.3.3.11 Data Transfer Interrupt Handling in xmc4500_rm_v1+2_2012_12) for the definition of UART RI and AI, thanks.

Best regards,
Sophia
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Sophia,

thanks for your answer. It is no Problem to generate an Interrupt for one Byte.

Since we have a fifo, you really do not want to have an Interrupt for every Byte. Setting the Trigger Level to some value will give you the
Chance to receive an Interrupt when the filling Level is reached.

When the filling Level int is fired the Service Routine will get all the Bytes in the fifo and puts them somewhere,
But what if f.e. the Trigger Level is set to 8 Bytes and there is only one Byte in the fifo ?
You will never receive an Interrupt for this Scene.

Fifo is made to reduce the Interrupt payload. How do I get something like a timeout Interrupt to get this one Byte ?
It cannot be to have an Interrupt for every Byte and for reaching the Trigger Level. This just makes no sense.
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Hi VTrapp,

Since you have set the trigger level to 8 byte for example, there is no way an interrupt is triggered before the FIFO reached 8 bytes.
So if you want something like a timeout, you may use CCU4 or system tick to act as a time based trigger for you to check on the FIFO level.
Then in the interrupt, you can read out any received data if the FIFO is not empty.
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Thanks Jackson,

so there is no way to reduce Interrupt load by using the receive fifo.
Thats a Little strange !

I will try to findout if something like the 16550 timeout Interrupt can be done by using the CCU4.

Below is a section from the 16550 datasheet:

One side-effect of having a Rx FIFO is that the selected
interrupt trigger level may be above the data level in the
FIFO. This could occur when data at the end of the block
contains fewer bytes than the trigger level. No interrupt
would be issued to the CPU and the data would remain in
the UART. To prevent the software from having to check for
this situation the NS16550A incorporates a timeout interrupt.
The timeout interrupt is activated when there is at least one
byte in the Rx FIFO, and neither the CPU nor the Rx shift
register has accessed the Rx FIFO within 4 character times
of the last byte. The timeout interrupt is cleared or reset
when the CPU reads the Rx FIFO or another character enters
it.
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User10696
Level 4
Level 4
First solution authored
Hi VTrapp

Did you ever find a solution to this problem? I have got the same problem and need a solution.
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User10538
Level 3
Level 3
Good question, I've run into the same problem. When processing a streaming protocol, I can't wait forever on the FIFO getting full. It should be possible to check for data periodically.
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