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Hello,

I use a USIC in ASC mode (UART). Now I want to improve performance using a GPDMA.

What I want to do is: Software only writes to a memory buffer and starts sending. GPDMA sends data continously to USIC until everything is sent. How do I achieve this?

The manual mentions a lot of things. There are the terms flow control and handshaking. What configuration do I need? The DMA003 seems not very helpful. In my mind I would need the DMA Line Router to make the USIC the DMA inform whether he can accept data. But which thing is the flow controller? A sample code would be quite helpful. Or at least a description how to do this.

// EDIT: The next thing is that the UART uses FIFO (32 byte for receive, same for transmit). So if UART is the trigger, I need to map a SRx from USIC. But which "event" should go to the SR.

Kind regards,
Christian
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23 Replies
Not applicable
Hi,
I think you want to trigger the DMA on the shift register empty or data transfer complet event. Then the DMA transfers the next data to the shift register then the selectet event occours. What you need to do:
Read in the reference manual the chapters about the DMA especially the corresponding part about flow control and the chapter about the USIC how to generate a request to the DMA.
Because I don't use DAVE Apps I can't tell you which App fits best in your design.
Regards Jannis
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Hi,

I will try to code this on myself.

Regards
Christian
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Hi Christian,

I have forwarded your question to our colleague who will give you some advice at a later time as he has some urgent task on-hand.

Best regards,
Sophia
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Hi Sophia,

this is good. The delay is no problem, as I am working on another task too.

Kind regards,
Christian
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jferreira
Employee
Employee
First like received 750 replies posted 500 replies posted
Hello Christian,

I have attached an example Dave3 project showing how to transfer an SRAM buffer (1KB in the example) to the USIC FIFO.

In this case the flow control is done by the GPDMA since the block size is known prior to when the DMA channel is enabled. The GPDMA will disable the DMA channel once the complete block is transmitted.
The SRAM does not need any handshaking (i.e. dma_req or dma_ack).
In the other hand the USIC in this example is using a hardware handshaking to indicate the DMA when it can accept more data, based on the FIFO fill level.
The transmit buffer of the FIFO is configured with 32 words.

The DMA will send 32 bytes as soon as the USIC request it. See the initial software triggering of the USIC service request (that is connected to the GPDMA using the DLR)
Then the USIC will start the transmission flushing the FIFO. Once the FIFO level is below the limit of 1, it will make a new request to the DMA that will be served immediately.
The process continues until the full 1KB is transmitted.

Please let me know if you have further questions and whether the example fulfills your needs.

Best regards,
Jesus
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Jesus,

How does one reverse this and transfer from a UART receive buffer to a DMA?
Also, why can't UART001_Handle0.UartRegs->IN be defined in the DMA003 UI?
The dstBuffer varaible looks to be a placeholder.

Thanks,
Doug
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jferreira
Employee
Employee
First like received 750 replies posted 500 replies posted
Hi Doug,

Find attached an example transferring data from UART to SRAM using DMA.
The DMA is configured to transfer a block of 1024 bytes.
You can also find attached a Python program to test the transfer (thanks to Eli Bendersky for the eblib, check at http://eli.thegreenplace.net/category/programming/python/ )
The micro will check the frame received and if successful will turn on the led.

Regarding your UI question, this is something we are going to fix in a new release of the app.

Do not hesitate to contact again in case of further questions.

Best regards,

Jesus
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I test the projects and report back then. Thank you very much!

// EDIT: This seems quite simple, if one uses the appropriate DMA app. What I did not find clear in the code: How is assured that the DMA does not write to FIFO if there is no space? Or is this done by the hardware handshake of the UART? There is only the hardware handshake enabled. Does this mean all the other things like that FIFO filling level is used in this case, is configured automatically?
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jferreira
Employee
Employee
First like received 750 replies posted 500 replies posted
Hi Christian,

The USIC tells the DMA when it can accept more data.

When the peripheral interrupt handshaking interface (hardware handshaking in the UI) is used an interrupt line from the peripheral (via DLR) is tied to the dma_req input of the hardware handshaking in the DMA.
In this case, the interrupt line is the service request triggered by the USIC when the transmit FIFO level fall below a certain limit (configured in the UART001 UI, i.e. 1).
So any time the USIC transmit FIFO is empty it will trigger an interrupt requesting more data from the DMA.

I hope this answer your question. Do not hesitate to contact again in case of further questions.

Best regards,
Jesus
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Not applicable
If a two separate DMA003 apps are being used for the transmit and receive of a single communication app, UART001 or I2C001, are two separate NVIC001 apps required?
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User7688
Level 2
Level 2
any example with 2 uart transferring the same time?
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Hi Edgardo,

Our colleague will prepare an example for this use case.

Best regards,
Sophia
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Hi,

I updated the apps in the examples postet in this thread. But then it didnt run how it should.
Are there any examples with the updated apps?
Especially UART to DMA.
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Hi,

Have you tried "UART001_Example4_XMC44"?

BR,
Zain
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Thanks for the DMA->UART Example. This works fine.
Someone can publish a working UART->DMA code?
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Hi Christian,

Our colleague is look into this and will provide an example.

Best regards,
Sophia
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Hi,

i have a nearly good working code. But there is still one problem:

I'm reading from UART to DMA into the array "Buffer[3000]". At some point of the code, i want to delete the data stored in the Array (no Problem) and start writing to Buffer[0] again.
I couldnt find a pointer or something to do that. What I have to manipulate to have success?
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Hi,

Have you tried to change the "Block Size" in DMA003 "Channel Configuration" tab?

BR,
Zain
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Hi,

and thanks for the answer but changing the Block Size does not help.
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Hi,

Not sure whether you can use "Linked list multi-block transfer with auto-reload DAR"? There is a simple start "XMC_HOT: XMC4500:How to do Multi BLK DMA transfer (SRC Linked list n DST contiguous)?"

BR,
Zain
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haakonsbakken wrote:
Hello Jesus,

Well, yes. CH_SUSP does suspend a DMA channel. And, I finally found a way to solve this which involves suspending each channel until none are running, then disable the DMA IRQ (otherwise the interrupt is immediately active as there are no data to transfer, causing no other code to be reached). To be able to restart the whole thing I also need to disable the DMA channels (CHENREG), set the DAR, reset CH_SUSP, reenable DMA channels (CHENREG, MASKBLOCK, CLEARBLOCK), clear pending DMA IRQs and reenable DMA IRQ. In addition, support has suggested stopping and restarting the VADC groups as part of this procedure. Phew!

Thanks, anyway. 😮
/Åse Maj

(http://www.infineonforums.com/threads/1536-Correct-way-to-suspend-stop-and-later-restart-DMA?p=4192&...)

seems to work. When "everything is down" you can change the Destination address.
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Hi,

New Question:

Szenario: I've got an text to put out of UART. The length is variable and >64B. The solution is GPDMA Transfer with Software Handshaking?! Is there another way to success?
Someone got a little example code for Software Handshaking DMA->UART?

All the examples I can find use Hardware Handshaking and a fixed Output length.
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User9239
Level 1
Level 1
I am also interesting in some example code regarding the question above? Please could anyone help?
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