UART App for XMC4500

[#1]

I'm in the process of getting up to speed on DAVE and the XMC4500.
I'm moving an application from a Freescale processor the the XMC4500.

The old processor had a library of functions to handle interrupt driven UART communication.
You could specify a large Tx buffer and an Rx buffer in RAM and there were functions to handle the UART interrupts and store the data in the Rx and Tx FIFO's etc.

The API interface used functions like TransmitBlock, ReceiveBlock, etc to move data to/from the RAM FIFO's and the UART.

I've been looking at the Apps for the XMC4500 such as UART001.
I'm not seeing anything to handle block transfers and the FIFO's etc.

Is this code that I'll have to write myself or am I overlooking something.

Thanks,
Kirk

[#2]

Hi Kirk,

Thank you very much for your interest on XMC4500.
First of all, i would like to confirm that there is no similar function of moving data to/from the RAM FIFO's and the UART in XMC4500. The USIC module itself has the FIFO buffer capability. The total buffer capability is 64 data words sharing between receive and transmit FIFO buffers of a USIC module. The two channels of the USIC module share the 64 data word buffer. You could refer to Pg1564 of "xmc4500_rm_v1+2_2012_12_" for more details.
It seems that your application requires large buffer. How much is it? Does your application require the UART communication keeping on all the time?

Best regards,
Sophia

[#3]

Hi Sophia,

We're using about 1k byte Tx and Rx buffers.
In the Tx direction the application communicates a stream of bytes at 2M baud.
The device receiving the Tx data sometimes stops the flow for significant amounts of time.
The source of the data is a real-time sampling that cannot be stopped, thus the need for the buffer.

In the Rx direction the application must be able to accept UART data at any time. The processor may be busy and the Rx data needs to accumulate under interrupt until it is handled.

The required size of the Rx buffer may get somewhat smaller because the XMC4500 is a faster processor.
The Tx buffer size depends on how long the pauses are and the speed of the sampling.

I'm really looking for some ideas on how to proceed.

Are you aware of some 3rd party librarys that will solve this?

Do you think using DMA with the UART is a good idea?

We're considering using an RTOS and I'm wondering how this will affect the implentation of the UART data handling code?

Thanks for your help with this,
Kirk

[#4]

Hi Kirk,

Maybe you can try to use DMA (multi-block transfer function) with UART via peripheral interrupt hardware handshaking interface. USIC receive/transmit FIFO fill level can be used to trigger interrupt requests for data transfer to/from the DMA. There are some examples available for the single block transfer (UART and GPDMA) as well as the multi-block transfer (DMA002 - Linked list multi-block transfer).

Best regards,
Sophia

[#5]

Sophia,

I'll dig into the examples to see what I can come up with.
Thanks,
Kirk