SPI Slave Mode - How to configure clock polarity (CPOL) and phase (CPHA) ???

[#1]

I'm trying to set up an SPI slave with my XMC 2Go (XMC1100). There are no options for configuring the clock polarity and phase. Would I be better off scrapping the whole DAVE App bs and just code the whole thing from scratch? That seems like a daunting exercise - I've spent hours and hours trying to read the data sheet for the XMC1100. It is barely comprehensible and I inevitably need to look away or take a nap... Support from Infineon seems to be non-existant and there are more questions than answers on this forum.

[#2]

Really??? Infineon has no presence here and I can get no answers? Time to move on after wasting way too much time with Infineon...

[#3]

Hi,

Are you looking for BRG.SCLKCFG (Shift Clock Output Configuration), eg. USIC0_CH1 -> BRG |= 0xC0000000?

BR,
Zain

[#4]

Zain wrote:
Are you looking for BRG.SCLKCFG (Shift Clock Output Configuration), eg. USIC0_CH1 -> BRG |= 0xC0000000?

Considering the fact that I am configuring an SPI Slave, I don't know why I would be concerned about Baud Rate Generation.

Since this is the DAVE forum, this question relates directly to the use of DAVE and DAVE apps. In most of the real world "SPI Mode", "CPOL", and "CPHA" have meaning when configuring an SPI port, whether for master or slave operation. This does not seem to be the case in the land of DAVE/Infineon. The only option in the SPI003 UIEditor is "Enable Slave Select Input Polarity", the vagueness of which deserves a thread of its own. Therefore, my question stands:

How do I configure the slave SPI port mode (clock phase and polarity) using DAVE apps?
The short answer would seem to be "I don't".

Having said that, from what I have managed to decipher within the XMC1100 Reference Manual:
clock polarity (CPOL) is controlled by USIC0_CHn->DX1CR.DPOL
clock phase (CPHA) is controlled by USIC0_CHn->PCR.SSC_Mode.SLPHSEL

Since the DAVE app couldn't be bothered to configure these minor details, how do I go about doing it?
Is it OK to set these fields after DAVE_Init() has configured and enabled the port?
Should I modify SPI003.c and hope I never need to "Generate Code" again?

Anyone at Infineon care to join this conversation?

[#5]

clarkleach wrote:
Is it OK to set these fields after DAVE_Init() has configured and enabled the port?
Should I modify SPI003.c and hope I never need to "Generate Code" again?

It is ok to set these fields after DAVE_Init() in main.c. However, if you modify the SPI003.c, it will be overwritten after re-generating code.

BR,
Zain

[#6]

Hi Clark,

Thank you very much for the feedback.
As per Clock Polarity configuration, it has been planned (eTicket 412133003). At this time being, you can write "SPI003_Handle0.USICRegs->DX0CR |= USIC_CH_DX1CR_DPOL_Msk;" in the main.c after DAVE_Init(); as per Zain suggested. Then you will be able to regenerate code every time.

As for the Clock Phase (PCR.SLPHSEL), it is not working (refer to USIC_AI.007 in xmc1100_es_v1_6_2014_08). You need to adapt the phase waiting by software... This is the reason why we cannot add the Clock Phase configuration option to the SPI003 App.

Details pls refer to device guide "APP_XMC1000_XMC4000_USIC_V1_0" Pg30 3.3.1.2 Shift Clock (SCLK) and CS.



Best regards,
Sophia