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Not applicable
Hii Evry one,
I am trying to Implement SPI communication with XMC4500 Relax Kit Lite with out using DAVE Apps but with DAVE Development Environment, I am not able to access the registers with my initializations.
Is there a Special way to access the registers for accessing the USIC1_CH1 channel, is there a Pointer Problem in my code? after Debugging/ running too the Register values are always confined to 0xffff. is it not possible to Configure the SPI with out using DAVE apps?

void SPI_config( void )
{
// Disable SPI
USIC1_CH1->CCR &= ~( ((uint32_t)(0x01U & USIC_CH_CCR_MODE_Msk)));

// Enable SPI
USIC1_CH1->CCR |= 0x0001;


// Switch off the Baud rate generation for slave mode
USIC1_CH1->FDR=0;
USIC1_CH1->BRG=0;


// For Full duplex Configuration
USIC1_CH1->DX0CR |= (((1U << USIC_CH_DX0CR_INSW_Pos) & \
USIC_CH_DX0CR_INSW_Msk));


// HPCEN is Diabled
USIC1_CH1->CCR |= ((0U << USIC_CH_CCR_HPCEN_Pos) & \
USIC_CH_CCR_HPCEN_Msk);


/* Configuration of Protocol Control Register */
USIC1_CH1->PCR_SSCMode |=
(((0x00U & USIC_CH_PCR_SSCMode_MSLSEN_Msk)) | \
((0x00U << USIC_CH_PCR_SSCMode_SELCTR_Pos) & \
USIC_CH_PCR_SSCMode_SELCTR_Msk) | \
((0x00U << USIC_CH_PCR_SSCMode_SELINV_Pos) & \
USIC_CH_PCR_SSCMode_SELINV_Msk) | \
((0x00U << USIC_CH_PCR_SSCMode_CTQSEL1_Pos) & \
USIC_CH_PCR_SSCMode_CTQSEL1_Msk) | \
((0x00U << USIC_CH_PCR_SSCMode_PCTQ1_Pos) & \
USIC_CH_PCR_SSCMode_PCTQ1_Msk) | \
((0x00U << USIC_CH_PCR_SSCMode_DCTQ1_Pos) & \
USIC_CH_PCR_SSCMode_DCTQ1_Msk) | \
((0x00U << USIC_CH_PCR_SSCMode_MSLSIEN_Pos) & \
USIC_CH_PCR_SSCMode_MSLSIEN_Msk) | \
((0x00U << USIC_CH_PCR_SSCMode_SELO_Pos) & \
USIC_CH_PCR_SSCMode_SELO_Msk) | \
((0x00U << USIC_CH_PCR_SSCMode_TIWEN_Pos) \
& USIC_CH_PCR_SSCMode_TIWEN_Msk));


/* Configuration of USIC Shift Control */
USIC1_CH1->SCTR &= \
(~(uint32_t)(USIC_CH_SCTR_SDIR_Msk | USIC_CH_SCTR_FLE_Msk | \
USIC_CH_SCTR_WLE_Msk | USIC_CH_SCTR_HPCDIR_Msk | \
USIC_CH_SCTR_DSM_Msk));


/* Configuration of USIC Shift Control */
USIC1_CH1->SCTR |= \
(((1U << USIC_CH_SCTR_PDL_Pos ) & \
USIC_CH_SCTR_PDL_Msk ) | \
((1U << USIC_CH_SCTR_TRM_Pos ) & \
USIC_CH_SCTR_TRM_Msk ) | \
(((FrameLen - 1U) << USIC_CH_SCTR_FLE_Pos)\
& USIC_CH_SCTR_FLE_Msk ) | \
(((WordLen - 1U) << USIC_CH_SCTR_WLE_Pos) \
& USIC_CH_SCTR_WLE_Msk));



// DX0D is selected /* Configure P0.0 MTSR / U1C1.DX0D */
WR_REG(USIC1_CH1->DX0CR, (uint32_t)USIC_CH_DX0CR_DSEL_Msk, \
USIC_CH_DX0CR_DSEL_Pos,(uint32_t)3);


/* Configure P0.10, CLKIN (U1C1.DX1A) */
USIC1_CH1->DX1CR =
(0 << USIC_CH_DX1CR_DSEL_Pos) | // DX1A is selected
(1 << USIC_CH_DX1CR_INSW_Pos) |
(0 << USIC_CH_DX1CR_DFEN_Pos) |
(0 << USIC_CH_DX1CR_DSEN_Pos) |
(0 << USIC_CH_DX1CR_DPOL_Pos) |
(0 << USIC_CH_DX1CR_SFSEL_Pos) |
(0 << USIC_CH_DX1CR_CM_Pos) |
(0 << USIC_CH_DX1CR_DXS_Pos) ;


/* Configure P0.9, CS (U1C1.DX2A) Chip select */
USIC1_CH1->DX2CR =
(0 << USIC_CH_DX2CR_DSEL_Pos) | // DX2A is selected
(1 << USIC_CH_DX2CR_INSW_Pos) |
(0 << USIC_CH_DX2CR_DFEN_Pos) |
(0 << USIC_CH_DX2CR_DSEN_Pos) |
(1 << USIC_CH_DX2CR_DPOL_Pos) |
(0 << USIC_CH_DX2CR_SFSEL_Pos) |
(0 << USIC_CH_DX2CR_CM_Pos) |
(0 << USIC_CH_DX2CR_DXS_Pos) ;


/* Control P0.10 as Clock Input pin, Strong drive strength */
PORT0->IOCR8 = (PORT0->IOCR8 & ~ 0xF80000) | (0 << 19);
PORT0->PDR1 = (PORT0->PDR1 & ~0x700) | (2 << 8);

/* Control P0.9 as Chip select Input pin, Strong drive strength */
PORT1->IOCR8 = (PORT1->IOCR8 & ~0xF800) | (0 << 11);
PORT1->PDR1 = (PORT1->PDR1 & ~0x70) | (2 << 4);

/* Control P0.0 MTSR as Input pin, Strong drive strength */
PORT1->IOCR0 = (PORT1->IOCR0 & ~0xF8) | (0 << 3);
PORT1->PDR0 = (PORT1->PDR0 & ~0x7) | (2 << 0);

USIC1_CH1->CCR |= (((uint32_t)(0x01U & USIC_CH_CCR_MODE_Msk)));


}
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2 Replies
Not applicable
Hi Ravi,

Did you clear the reset for USIC1 by writing 1 to PRCLR1.USIC1RS (eg. SCU_RESET->PRCLR1 |= 0x80)?

BR,
Zain
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Not applicable
Hi Zain,

Thank you very much for the response, yes it was the reset, we need a USIC channel reset.






Best Regards,
Ravi
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