This sample code loops in the LPComp interrupt handler when a low voltage is detected, and stops the application operation below the detected voltage. The CSD operation is performed with Single IDAC, and low voltage detection is performed using another IDAC as the reference voltage of LPComp. It toggles the Pin_ACT_LED pin while scanning the CSD. When a low voltage is detected, the Pin_DET_LED pin is toggled in the LPComp interrupt handler. This low voltage detection causes an interrupt when VDD is about 4.0V or less and executes an infinite loop in the handler, but when VDD exceeds 4.2V, a software reset is executed. Moreover, the Nch MOSFET which accelerates the power consumption of VDD is controlled in order to improve the falling characteristic of VDD when it enters an interrupt.
In this waveform, VDD is down while scanning the CSD with the low voltage detection interrupt disabled. As you can see, the code is running even when VDD is about 1.55V. (Please refer to "Power On Reset (PRES)" and "Brown-out Detect (BOD) for VCCD" in the datasheet.)
By applying this code, you can stop the execution of the application when VDD becomes 4.0V or less. And you can also improve the power slew rate of the POR.
However, the best way to stop the application operation is to reset the XRES from the reset IC with the detected voltage.
This is a sample code that outputs 8ch PWM using CY8CKIT-149. The 8ch PWM outputs are connected as shown below. The blue wires should be wired.
You can use EZI2C to change the PWM duty from the Bridge Controll Panel of your PC. I attach the pwm_repeat.iic script file.
Click once in the Editor screen and press Ctrl + A to select all. Then click Repeat and the Compare value will change every 500ms.
Thanks and regards,
- S2GO PRESSURE DPS422 Evaluation Board
- PSoC 6 BLE Pioneer Kit CY8CKIT-062-BLE
- DPS422 datasheet (attached)
- GitHub repository for DPS422 Arduino Library
Operating Principle of the Sensor
- Pressure Measurement :
DPS422 makes use of a capacitive measurement principle. The sensor elements consist of a number of sealed vacuum cells. Each cell consists of a hollow, evacuated cavity with a flexible membrane sealing the top. The top membrane and the bottom of the cell are electrodes, which form a capacitor. Due to the pressure difference between the interior of the cell and the ambient environment, the top membrane is deflected towards the bottom of the cell. The vacuum cells are combined in a parallel measurement configuration, to increase the sensitivity and noise performance of the DPS422. Increasing ambient pressure causes greater deflection towards the bottom of the cell and hence and increase in the capacitance between the membrane and the bottom of the cell. Decreasing ambient pressure reduces the deflection of the membrane and reduces the capacitance between the membrane and the bottom of the cell. Pressure measurement is carried out by measuring the capacitance between the top and bottom of the cells and applying a calculation to the capacitance result to determine the pressure in Pa. It is also required to include a temperature correction in this calculation to eliminate temperature drift from the output.
- Temperature Measurement :
The DPS422 temperature measurement uses a silicon bandgap temperature sensor, measuring the base-emitter voltage (Vbe) of two BJT transistors, biased at different currents (IC1 and IC2). This measurement is used at a system level in the pressure output calculation to correct any temperature related measurement drift. The temperature of the transistors can be accurately determined by measuring the difference in voltage between both and applying the formula:
∆𝑉𝐵𝐸 = ((𝐾 × 𝑇) ÷ 𝑞) × ln(𝐼𝐶1 ÷ 𝐼𝐶2)
T is the temperature in Kelvin
K is Boltzmann's constant and
q is the charge of a single electron.
For step by step calculation of pressure and temperature values, refer to section 5.1.1 and 6.1 - 6.3 respectively, of the datasheet.
The purpose of this code example is to show the users how they can handle the different sector architecture types in Infineon serial NOR flash devices.
Tool: PSoC® Creator™ 4.4
Programming Language: C (Arm® GCC 5.4.1)
Software and Driver: Infineon Low Level Driver for SPI Flash
This example requires the PSoC 6 MCU’s VDD supply voltage to be set to 1.8V, since the FS-S NOR flash device family works at 1.8V power supply.
This example requires a serial terminal emulator such as PuTTY or Tera Term. Tera Term was used in this example.
Refer to KBA233140 Hybrid sector architecture of Infineon FL/FS-S serial NOR flash devices to get a better understanding of sector architecture.
The default configuration of the S25FS-S device can be determined by reading the third bit of Non-Volatile Configuration Register 3. The default value of CR3NV bit is 0 indicating hybrid sector architecture. When the device is in hybrid sector architecture mode, the Parameter 4 KB-Sector Erase command (P4E 20h) is used to erase the 4-KB parameter sectors. If Sector Erase command (SE D8h) is applied on the 4-KB parameter sector, it is not affected by the erase. The CR3NV bit is user programmable and can be set to 1 to change the device configuration to uniform sector architecture mode. However, this can be done only once as the bit is One Time Programmable (OTP). When the device is in uniform sector architecture mode, the overlay of the 4-KB parameter sectors is removed and all the sectors in the device are of uniform size (256KB). In this mode, the Sector Erase (SE D8h) command should be used to erase each individual sector and the Parameter 4 KB-Sector Erase command (P4E 20h) does not have any effect on the uniform sectors.
In this code example we have chosen the S25FS512S SPI NOR flash and interfaced it with PSoC 6 using SPI protocol.
Steps performed in the example:
- Initialize UART and SPI
- Read Device ID to make sure HW connections are okay
- Read 5 bytes from the starting address (0x000000). By default, the 4-KB parameter sectors are overlaid at the bottom location
- Program 5 bytes at starting location (0x000000)
- Read 5 bytes from starting location to confirm
- Erase first sector with P4E (0x20) command
- Read 5 bytes from starting location to confirm (erase is successful)
- Read CR3NV register
- If CR3NV bit is 0 (device is in hybrid sector architecture mode)
- Program 5 bytes at starting location
- Read 5 bytes from starting location to confirm
- Erase first sector with SE (0xD8) command
- Read 5 bytes from starting location to confirm (erase is not performed on parameter sector)
- Program CR3NV bit to 1 (change device configuration to uniform sector architecture mode)
- Read CR3NV register to confirm
- Erase first sector with SE (0xD8) command again
- Read 5 bytes from the starting location to confirm (erase is successful)
- Else if CR3NV bit is 1 (device is already in uniform sector architecture mode)
- Print that device is in uniform sector architecture mode
Design and Implementation
PSoC Creator Schematic:
Note: The Slave Select (SS) pin of the SPI block (SPIM_Flash) was disabled. The same pin (P12) was used as a GPIO (Flash_CS) in the project so that the flash CS# line can be controlled manually, as per the requirement of the Infineon sLLD.
When the example is executed on a fresh S25FS512S NOR flash device (CR3NV = 0)
When the example is re-executed on the same device (CR3NV = 1)
This project demonstrates Envelope Detection using a Hilbert transformer method.
The amplitude modulated sinusoidal carrier signal is sampled by DelSig_ADC, digitally processed to extract the AM envelope and outputted using VDAC8.
The envelope extraction is done using the Hilbert transformer method, utilizing the Filter component. Both channels of the Filter are preset with custom coefficients to form 63-point Hilbert band-pass filter, (0.1 to 0.9) x (Fs / 2), producing
analytical (vector) signal from the ADC data. Both channels are identical, except that Channel_A has added Hilbert phase +45 deg, and Channel_B has added phase of -45 deg, producing orthogonal vector (x,y), which magnitude (length) is proportional to the AM envelope amplitude.
The Filter coefficients are calculated using IowaHills Hilbert Filter Designer v3.0, which is available for download.
The vector length is calculated by CPU using CORDIC algorithm. To speed up processing, the procedure is restricted to only vector length (atan is ignored), and the number of iterations is reduced down to 6 (from 14), taking 58 clocks.
Optional custom Low Pass (moving average) filter can be applied to reduce step transition effects from the Hilbert filter.
The resulting envelope is sent to the VDAC8 and observed by o-scope.
Project includes optional test AM signal generator, which produces amplitude modulated signal at carrier frequency 23.4kHz. The signal generator is comprised of WaveDAC8, which is set to switch between the two Sine waves of different amplitudes, and PWM, which controls the AM period and duty cycle.
The Filter custom coefficients were produced using IowaHills Hilbert Filter Designer v3.0 by Iowa Hills Software LLC (IowaHills.com)
Project uses optional custom component MovingAverage Filter (included into the project) : MAFilter_v0_0
Figure 1. Project schematic. The Moving Average filter (Filter_1) is optional. Capacitor C_13 is a KIT-059 onboard capacitor, connected to Pin 0.
Figure 2. Optional signal generator, producing amplitude modulated signal at carrier frequency 23.4kHz. The WaveDAC8 is set to switch between the two Sine waves of different amplitudes. PWM controls the AM period and duty cycle.
Figure 3. Project annotation drafted using PSoC Annotation Library v1.0 . ADC is configured in differential mode. Capacitor C1 decouples signal generator from the ADC. Resistor R1 provides DC offset of 1.024V for ADC input (-). The signal generator is optional, it is not needed if an external AM signal is available.
Figure 4. IowaHills Hilbert Filter Designer v3.0. Filter coefficients for Channel A (Phase Add +45deg) are shown at the right pane. Channel B calculations are the same, except it uses Phase Add of -45deg (not shown).
Figure 5. Filter settings for Channel A. Filter coefficients are directly copied from the Hilbert Filter Designer.
Figure 6. Scope traces: Blue - input signal, Yellow - envelope output, Cyan - reference. AM amplitude 1.0V, amplitude modulation 50%. Carrier frequency 23.3 kHz, AM frequency 0.583 kHz (PWM Period=40). The output is delayed by the Filter by (63-1)/2 samples.
Figure 7. Scope traces: Blue - input signal, Yellow - envelope output, Cyan - reference. AM amplitude 1.0V, amplitude modulation 50%, AM frequency 2.33 kHz (PWM Period=10). Carrier frequency 23.3 kHz.
Figure 8. Scope traces: Blue - input signal, Yellow - envelope output, Cyan - reference. AM amplitude 0.012V, amplitude modulation 50%, AM frequency 2.33 kHz (PWM Period=10). Carrier frequency 23.3 kHz. The output (Yellow trace) is digitally scaled up by 32 to match 8-bit scale of VDAC8.
This post is for a multi- stepper motor control (up to 8 in this example) using minimum PSoC resources. This allows for reasonable control of the PWM pulses for stepper motors across virtually all PSoC MCUs with fewer HW resources.
The architecture to accomplish this is that there is one PWM in continuous run mode with the pulse ratio required for the stepper motors. The application turns on individual motors by defining which motor and how many pulses. The PWM generates an ISR to count down the pulses loaded until '0'. When the count is '0', the motor is turned off.
- Turns on certain motors for specific counts.
- It waits for all motors to stop.
- Waits for 10ms
- Turns on other motors for specific counts.
- It waits for all motors to stop.
- Waits for 10ms
- Repeat this pattern ...
I've uploaded 4 projects for the PSoC3, PSoC4, PSoC5 and PSoC6 MCUs. These projects were targeted for popular Infineon kits and eval boards but can be easily modified to run on most HW.
The stepper motor pulse ratio is adjustable and the ON count is assigned by an API call.
This example is designed to quickly (all 4 versions took 6 hours to create and debug) create stepper motor pulses to multiple stepper motors independently. However, I do not have certain safety functions such as emergency stops that may be required for some systems. This project is a starting point for your applications such as a CNC machine or a 3D printer. It's now up to YOU!!!
I support 8 stepper motor outputs because that is what would fit in one PSoC control register. You can extend to to more ports with more sophisticated coding.
These projects require PSoCs with some UDB resources. PSoCs without UDBs but have SmartIOs should be able to support a similar architecture.
Anyone interested in converting this project to SmartIOs?
No code changes. Just updated the name of the projects to reflect the 8 channel Stepper Motor.
Added an additional project 8_StepperMotor_SW_PSoC63.cyprj.Archive01 which compiles and runs on the CY8CPROTO-063-BLE eval board.
I've uploaded an example project that illustrates very efficient ISR coding of 11 UART Rx ports.
It is uses a SW circular FIFO buffer for each port with threshold detection of a message size (in this case 7 bytes) and FIFO buffer overrun.
With my implementation I can achieve nearly 300KBaud for each of 11 Rx ports with the BUS_CLK @ 79.5MHz. I can achieve 100KBaud with BUS_CLK at 24MHz.
This example is intended to be a starting point for your next project for very high performance data acquisition that also supports some error detection.
- PSoC Creator 2.0 or higher.
- Many PSoCs with some minor modifications.
The project was created on a CY8CKIT-059 but can be built on virtually any PSoC5 platform.
Included is a document file explaining the project goals and a treatise on Interrupts.Show Less
I'm attaching a project which includes a pre-component version of a 14-bit VDAC using the dithering method to generate the extra bits of resolution beyond the inherent 8-bits provided by the Cypress VDAC8 component.
In principle it is identical to the Cypress DVDAC (12-bits max resolution) in theory of operation. It even has the same API calls.
Besides having 2 additional bits of resolution (max 14-bits), it doesn't use the DMA to operate the dithering. Instead it uses a 100% HW state machine created with UDBs. Therefore, the dithering is always in-sync to the VDAC clock and is not prone to DMA latencies. In fact, it uses 0% CPU cycles to keep it running!
Project SW Requirements:
- PSoC Creator 4.2.
- Use project DVDAC14_Demo_PSoC5
- The project supplied is designed to run on a stock CY8CKIT-059 with NO EXTERNAL components!
- The project can be modified to run on other PSoC5LP-based designs. (eg CY8CKIT-050, SparkFun boards, etc.)
- Use project DVDAC14_Demo_PSoC3
- The project supplied is designed to run on a stock CY8CKIT-030 with the addition on one small capacitor.
- The project can be modified to run on other PSoC3-based designs.
he project attached is a Demo code example that allows for user modify the DVDAC14 'component' parameters through the API calls to the included pre-component.
The Demo project uses my Term, MenuCmds and String_Funcs components to simplify the user access to the run-time features.
I have include the needed component libraries as imported into the project for your convenience.
Here is a link to my component library: Terminal-Support-Component-Library if you'd prefer to use these components as a shared resource for your other projects.
Why do this?
Because you (more specifically ... I) can. Cypress demonstrated that this is possible with their DVDAC12. I extended their idea to a HW-only solution as a learning experience and possibly a teaching tool to help show the value of the PSoCs that have UDBs. It has been my experience as an engineer that if you can move highly repetitive operations into a HW state-machine, you can achieve significant performance gains.
There might be some of you that ask: Can the DVDAC be made to support 16-bits? The short answer is yes. However, in this style of implementation you would need 32 UDB blocks. This would deplete your UDB resources. Additionally, the extra VDAC sensitivity virtually gained would be outweighed by the noise in practically any system.
I have released the DVDAC14 as a pre-component. It has about 80% of the component structures including the API calls.
I'm looking for user feedback. This includes implementation bugs if you find some. If you have some suggestions, I'd welcome the input.
Once I feel the pre-component version is stable I would consider making it into a full-fledged component.
Happy Holidays and Enjoy!Show Less
This sample code implements SmartIO's Count Up Wrap function using a Divided Clock.
The Clock component is connected to the clock of SmartIO2.
GND is connected to TR0 (rst) and VDD is connected to TR1 (en) of Count Up Wrap, but since it cannot be directly connected, it goes through LUT0 and LUT1, respectively.
DU is a Count Up Wrap function, and the counter outputs a pulse with 6 counts match of 8bit counter.
The output of DU is registered out to gpio6 with LUT6 .
2_1 is connected to VDD and P2_0 is connected to GND by external wiring.
The following waveforms can be observed after programming.
Pin_PWM_CLK (P3_6) is a clock for waveform observation with an oscilloscope.
And note that the Clock component output is divided by two.