I have posted this sample code to check the waveform of the RESET pin and the values of the registers affected by WDT1 RESET/ SYS_FAIL RESET.
Using this sample code, you can see the following :
1, You can check the SYS_FAIL RESET period by your oscilloscope.
2, You can check the WDT1 REST by your oscilloscope.
3, You can check value of both PMU_RESET_SYS and PMU_WFS registers by the terminal software on your PC.
Confirmed evaluation boards :
1) TLE984x Evalboard
2) TLE9844-2QX Application Kit
1) Program this software into your evaluation board via uVision.
2) Execute any terminal software on your PC (ex. TeraTerm) and connect it with evaluation board at 115200bps.
3) Push RESET-SW on the evaluation board.
Then, you can see the register values by terminal software and RESET-pin pulse by oscilloscope, every RESET timing.
1, SYS_FAIL RESET waveform :
You can see a 1sec of Fail Sleep period. Please refer to the waveform in the left.
2, WDT1 REST waveform :
In this code, WDP_SEL=0x3F(1.008sec). So, you can see 4 times of 32us glitch pulse. Please refer to the waveform in the bottom right. And the 5th time, Fail Sleep RESET can be confirmed.
About WDT1 RESET pulse :
I was surprised because I haven’t noticed that there is a RESET mode which RESET-pin will not be asserted.
WDT1 (Watchdog) RESET is that one. And I coudn7t find out such an explanation in the UM v1.3.
By the way, explanation of TLE987x UM v1.8 is almost same.
However, we have observed on the oscilloscope that the TLE987x does not assert the RESET pin at all when WDT1 occurs.
About SYS_FAIL RESET pulse :
TLE987x_UM has the following sentence.
However, there isn’t any explanation why the waiting time is 1 sec.
TLE987x_UM, Rev1.8, p22,
Sleep mode is activated after 5 consecutive watchdog failures or in case of supply failure (5 times). In this case,
MON is enabled as the wake source and cyclic wake-up is activated with 1 s of wait time.
There is no such statement in TLE984x UM v1.3, but I guess the same from my measurement results.
And about 1sec of the wait time, TLE987x_UM and TLE984x_UM have no description.
However, I think the SYS_FAIL period can be calculated with the default value of the PMU SLEEP register.
The off-time of the Cyclic mode is calculated to be 1.024 sec.
3, Value of both PMU_RESET_SYS and PMU_WFS registers of every RESET:
You can see the value of both registers as the below.
If you have any feedback, please let me know.