Uniform and Hybrid Sector Architecture Configurations of S25FS-S SPI NOR Flash

[Apurva_S]

Overview

The purpose of this code example is to show the users how they can handle the different sector architecture types in Infineon serial NOR flash devices.

Requirements

Tool: PSoC® Creator™ 4.4

Programming Language: C (Arm® GCC 5.4.1)

Related Hardware: S25FS512S SPI NOR flash memory, PSoC 6 BLE Pioneer Kit

Software and Driver: Infineon Low Level Driver for SPI Flash

Hardware Setup 

This example requires the PSoC 6 MCU’s V_DD  supply voltage to be set to 1.8V, since the FS-S NOR flash device family works at 1.8V power supply.

Software Setup

This example requires a serial terminal emulator such as PuTTY or Tera Term. Tera Term was used in this example.

Operation

Refer to KBA233140 Hybrid sector architecture of Infineon FL/FS-S serial NOR flash devices to get a better understanding of sector architecture.

The default configuration of the S25FS-S device can be determined by reading the third bit of Non-Volatile Configuration Register 3. The default value of CR3NV[3] bit is 0 indicating hybrid sector architecture. When the device is in hybrid sector architecture mode, the Parameter 4 KB-Sector Erase command (P4E 20h) is used to erase the 4-KB parameter sectors. If Sector Erase command (SE D8h) is applied on the 4-KB parameter sector, it is not affected by the erase. The CR3NV[3] bit is user programmable and can be set to 1 to change the device configuration to uniform sector architecture mode. However, this can be done only once as the bit is One Time Programmable (OTP). When the device is in uniform sector architecture mode, the overlay of the 4-KB parameter sectors is removed and all the sectors in the device are of uniform size (256KB). In this mode, the Sector Erase (SE D8h) command should be used to erase each individual sector and the Parameter 4 KB-Sector Erase command (P4E 20h) does not have any effect on the uniform sectors.

In this code example we have chosen the S25FS512S SPI NOR flash and interfaced it with PSoC 6 using SPI protocol.

Steps performed in the example:

1. Initialize UART and SPI
2. Read Device ID to make sure HW connections are okay
3. Read 5 bytes from the starting address (0x000000). By default, the 4-KB parameter sectors are overlaid at the bottom location
4. Program 5 bytes at starting location (0x000000)
5. Read 5 bytes from starting location to confirm
6. Erase first sector with P4E (0x20) command
7. Read 5 bytes from starting location to confirm (erase is successful)
8. Read CR3NV register
9. If CR3NV[3] bit is 0 (device is in hybrid sector architecture mode)
   1. Program 5 bytes at starting location
   2. Read 5 bytes from starting location to confirm
   3. Erase first sector with SE (0xD8) command
   4. Read 5 bytes from starting location to confirm (erase is not performed on parameter sector)
   5. Program CR3NV[3] bit to 1 (change device configuration to uniform sector architecture mode)
   6. Read CR3NV register to confirm
   7. Erase first sector with SE (0xD8) command again
   8. Read 5 bytes from the starting location to confirm (erase is successful)
10. Else if CR3NV[3] bit is 1 (device is already in uniform sector architecture mode)
    1. Print that device is in uniform sector architecture mode

Design and Implementation

Connections:

S25FS512S Flash	CY8CKIT-062-BLE
MISO	P12[1]
MOSI	P12[0]
SCK	P12[2]
CS#	P12[3]
VCC	P6_VDD
VSS	GND

PSoC Creator Schematic:

Note: The Slave Select (SS) pin of the SPI block (SPIM_Flash) was disabled. The same pin (P12[3]) was used as a GPIO (Flash_CS) in the project so that the flash CS# line can be controlled manually, as per the requirement of the Infineon sLLD. 

Expected Output:

When the example is executed on a fresh S25FS512S NOR flash device (CR3NV[3] = 0)

When the example is re-executed on the same device (CR3NV[3] = 1)

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