Status Register polling for Infineon SPI NOR Flash

[Ronak]

Overview

The purpose of this code example is to show the users how Status Register polling is done on Infineon serial NOR flash devices.

Requirements

Tool: PSoC® Creator™ 4.4

Programming Language: C (Arm® GCC 5.4.1)

Related Hardware: S25FS512S SPI NOR flash memory, PSoC 6 BLE Pioneer Kit

Software and Driver: Infineon Low Level Driver for SPI Flash

Hardware Setup

This example requires the PSoC 6 MCU’s V_DD  supply voltage to be set to 1.8V since the FS-S NOR flash device family works at a 1.8V power supply.

Software Setup

This example requires a serial terminal emulator such as PuTTY or Tera Term. Tera Term was used in this example.

Operation

To start any new operation on flash the previous operation must be completed without any errors. After every program and erase operations, status register is polled to check completion status and status of error bits.

In Infineon SPI NOR Flash the status register, in general, have bits assigned to indicate programming error and erase error. In this example, S25FS512S was used, in which the  seventh bit of status register 1 (SR1[7]) is Programming error status bit and  sixth bit of status register 1 

(SR1[6]) is Erase error status bit. If any of the two bits are set, then the user can understand that during the flash operation what error had occurred.

In this example, a polling function is called to perform the repeated operation of polling after every program/erase operation. The polling function consists of an infinite loop that checks if the P_ERR or E_ERR bits are set till the WIP (Write in progress) bit of the status register is 1. Once the WIP bit gets changed to 0, it can be concluded that no error has occurred in the flash operation.

In this code example, we have chosen the S25FS512S SPI NOR flash and interfaced it with PSoC 6 using the SPI protocol.

Steps performed in the example:

1. Initialise UART and SPI
2. Read Device ID
3. Program to the location of 0x040000
4. Call the polling function
5. Erase the sector starting at memory location 0x040000
6. Call the polling function
7. Write to the Status register to implement Block protection. Read the status register to confirm
8. Program to the location of 0x040000 (program is unsuccessful)
9. Call the polling function
10. Clear the Status Register
11. Erase the sector starting at memory location 0x040000
12. Call the polling function
13. Clear the Status Register
14. Write to  the Status Register to remove the Block protection. Read the status register to confirm

Design and Implementation

Connections:

S25FS512S Flash	CY8CKIT-062-BLE
MISO	P12[1]
MOSI	P12[0]
SCK	P12[2]
CS#	P12[3]
VCC	P6_VDD
VSS	GND

PSoC Creator Schematic:

 Note: The Slave Select (SS) pin of the SPI block (SPIM_Flash) was disabled. The same pin (P12[3]) was used as a GPIO (Flash_CS) in the project so that the flash CS# line can be controlled manually, as per the requirement of the Infineon sLLD. 

Expected Output:

When the example is executed on S25FS512S NOR flash device we get the following output