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Code Examples

Len_CONSULTRON
Level 9
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Level 9

Hi,

I've uploaded an example project that illustrates very efficient ISR coding of 11 UART Rx ports.

It is uses a SW circular FIFO buffer for each port with threshold detection of a message size (in this case 7 bytes) and FIFO buffer overrun.

With my implementation I can achieve nearly 300KBaud for each of 11 Rx ports with the BUS_CLK @ 79.5MHz.  I can achieve 100KBaud with BUS_CLK at 24MHz.

This example is intended to be a starting point for your next project for very high performance data acquisition that also supports some error detection.

Requirements:

  • PSoC5LP
  • PSoC Creator 2.0 or higher.
  • Many PSoCs with some minor modifications.

The project was created on a CY8CKIT-059 but can be built on virtually any PSoC5 platform.

Included is a document file explaining the project goals and a treatise on Interrupts.

Len
"Engineering is an Art. The Art of Compromise."
3 Replies
AlenAn14
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator

Hi @Len_CONSULTRON ,

Thank you for this very useful contribution to our PSoC Family.
We highly appreciate the effort you have put into the project and the well detailed documentation provided in the same.
Please continue to contribute such insightful examples and coding practices in the community 😊.

Thanks & Warm Regards
Alen

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odissey1
Level 9
First comment on KBA 1000 replies posted 750 replies posted
Level 9

Len,

I suggest adding the project description (Multi_RxIsr_Example_v1_0.pdf) directly in the attachment, so that anyone interested can read it without downloading the entire project archive.

P.S. As a comment to the Interrupts saga, I am aware of at  least two modern microprocessors, which use no interrupts: the Parallax Propeller 1/2, and XMOS. Both use multi-core processing (8+), so that separate tasks can be served without interruption.

 

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Len_CONSULTRON
Level 9
1000 replies posted 750 replies posted 500 likes received
Level 9

odissey1,

I placed the pdf as a separate attachment as you suggested.  Excellent suggestion.

I was not aware of those processors.

My first guess is that when an event occurs (that would be considered an interrupt on most processors) it is processed on one of the extra cores.  It is either handled in a polling structure on that core or if the core can be halted, it wakes up the core to process the event.

Len
"Engineering is an Art. The Art of Compromise."
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