Glitchless PWM

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Ritwick_S
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100 solutions authored 25 likes received 250 sign-ins

Overview

This code example shows how to generate glitch less PWM using CompareBuf and PSoC4 devices. This example demonstrates interrupt and DMA methods. For further clarification on the term “Glitchless, please go to “Additional sections”.

Requirements

Tool: PSoC® Creator™ 4.4

Programming Language: C (Arm® GCC 5.4.1)

Associated Parts: PSoC 4 family; DMA example only works with PSoC 4 devices with DMA

Related Hardware:

 

Operation

  1. Open the PWM project.
  2. Connect the PSoC 4 kit to your computer using USB cable.
  3. Make sure that the required project is set as the active project; right-click the project and select Set As Active Project.
  4. Build the project that corresponds to that specific board and program it onto the PSoC 4 device. Choose Debug > Program. For more information on the device programming, see PSoC Creator Help.
  5. To observe the PWM waveform, probe the “PWM Output pin”.

Design and Implementation

An array that contains the desired compare values is updated at the terminal count of the UPDATE timer block. There is a PWM block and an UPDATE timer block. When the update timer is expired, a new compare value from that array is written into the comparebuf register. Based on the switch event, there are two projects showing different ways of switching, i.e., software and hardware switch.

  • Interrupt

When the update timer is expired, isr_PWM_UPDATE gets triggered. In the interrupt handler function COMP_UPDATE_InterruptHandler(), the next compare value from the array is written into the comparebuf register and then, a software trigger is given to swap the compare and comparebuf registes values at the TC event. This implementation uses a software switch event, as the trigger is through the firmware.

Figure 1 shows the top-level design of the Glitchless_PWM_Interrupt example project:

ritwicksharma_21-1650284055937.png

 

Figure 1 Glitchless_PWM_Interrupt Top Design Schematic

 

 

ritwicksharma_22-1650284077635.png

Figure 2 Timer Configuration for Interrupt project

  • DMA

When the update timer counter becomes equal to PERIOD, the overflow signal is triggered that is used to trigger a DMA transfer, which writes the compare value into the comparebuf register. And on completion of a transfer, tr_out is triggered that is connected to the switch input of the PWM component, which acts as a hardware trigger signal that swaps the compare and comparebuf registers values at TC event.

Figure 3 shows the top-level design of the Glitchless_PWM_DMA example project:

 

ritwicksharma_24-1650284124094.png

 

Figure 3 Glitchless_PWM_DMA Top Design Schematic

ritwicksharma_25-1650284124099.png

Figure 4 PWM Tab Configuration for DMA project

 

ritwicksharma_27-1650284492834.png

 

ritwicksharma_28-1650284492841.png

Figure 5 DMA configuration Settings

 

Related Resources

Application Notes

[1] AN79953 – Getting Started with PSoC® 4: Describes PSoC 4 devices and how to build your first PSoC

Creator project

PSoC Creator Component Datasheets

[2] DMA: Supports direct memory access (DMA) controllers

[3] TCPWM: Supports Timer/Counter, PWM, and Quadrature Decoder

Development Kit Documentation

[4] CY8CKIT-042 PSoC 4 Pioneer Kit

[5] CY8CKIT-044 PSoC 4 M-Series Pioneer Kit

[6] CY8CKIT-045S PSoC 4500S Pioneer Kit

[7] PSoC 4 Kits

Tool Documentation

[8] PSoC Creator: Look in the downloads tab for Quick Start and User Guides

 

Additional Section

Below is the image which explains the term glitch. The one circled in red is a glitched pulse. When the new compare value is smaller than the current value in the counter, the counter will run until the maximum possible value and then roll over to zero. Only then the new compare value would come into effect. So here, in our case, the new compare value is 10, and the current counter value is greater than 10. Hence, there is an extended period, as the counter runs up to 64 and then rolls over to zero.

ritwicksharma_48-1650285226345.png

 

 

There are three cases, i.e., pwm_period = update_timer_period, pwm_period < update_timer_period, and pwm_period > update_timer_period.

 

    • pwm_period = update_timer_period

    In this case, you won't find any repeated pulse as the PWM and update_timer are in sync.

 

  • ritwicksharma_50-1650285340668.png

    • pwm_period < update_timer_period

    In this case, you will sometimes find a pulse less than expected. As per code, one pulse of each is expected. The part circled in red is not as expected. There is no 25-compare value pulse as the 40-compare value update came before the 10-compare value cycle ended.

     

    ritwicksharma_51-1650285371731.png

     

     

    • pwm_period > update_timer_period

    In this case, as the update pulse came after the 25-compare value pulse started, therefore, a 25-compare value cycle is repeated, and at the next TC event, the new compare value is updated, i.e., 40.

     

    ritwicksharma_52-1650285391643.png

     


     
2 Replies
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Thank you for demo project. Is PSoC5 PWM (UDB) also prone for the Counter or Period update glitches? 

0 Likes

In my experience the PSoC5LP PWM (at least in FF) does show glitches like this.  I don't know if it's different in the UDB implementation.  Since I require smooth transitions for my applications (usually LED backlighting), I usually get around it by making any changes to the output DC in an ISR triggered by the Terminal Count (falling edge of PWM, when using "Less" for the compare type) and that clears it up.