Here I submitting my version of the 24-bit DDS arbitrary frequency generator component. It is useful for applications requiring precision frequency generation. Provided below are: component library, datasheet, application note and several demo projects exemplifying use of the component.
Many thanks to authors of various previous incarnations of DDSs: <PSoC73>, <pavloven>, <vdvorak>, <kabron>, <JLS1>.
This component was developed as part of Warp Verilog study and does not pursue any particular purpose.
Tried to import this component into my current project, but Creator failed to create the Community tab in the Component Catalog.
I'm not familiar importing components so any help would be appreciated.
To use the component add DDS24_lib dependency to the project, please follow this video for instructions:
1. Unzip DDS24_lib.zip
2. goto Project->Dependencies->Add library-> ..\DDS24_lib\DDS24_lib.cyprj. Done!
If you unzip both DDS24_lib.zip and DDS24_demos.zip in the same root folder, then all demos should recognize DDS24_lib dependency automatically, because it relies on a relative path.
Great, succeeded in importing your component.
Didn't find myself this way, but didn't go thru all the Cypress doc, my thanks for the help.
Do you plan to improve by including (all of the, or several) features you listed at the end of the datasheet?
I have modified your component and try to program it with CY8CKIT-050. In my program I wait for some iteration and changes the frequency (0-50Hz), but out freq displayed on my DMM is varying between 24-25Hz. Is there any problem with my setting.?
I made some changes to your project (see comments inside), it should work now.
Project is working, thanks I get your point.
But my question is what should I do for 0Hz (When frequency output control parameter is zero)? That is why I have used DDS_Stop(). Please see attachment, it is working as per expectation.
You put wrong component on schematic (DDS24_Core). This is "invisible" sub-component which incapsulates Verilog code only (no API). Use DDS24 component as shown in the WaveDAC8 example demo provided within DDS24_demos.zip file. Also, short explanation of the WaveDAC8 project can be found in DDS24 basic applications_AN-DDS24_00_A.pdf file.
I have loaded your DDS24 library for PSoC 4 BLE used, use hardcoded method, it is workable. I wish to use a 3.0 MHz clock source for DDS24, and it divided from external crystal 24.0 MHz on PSoC 4 BLE pioneer kit, Have I any chance to implement ?
1. What about size question, http://www.cypress.com/forum/psoc-4-ble/how-can-i-handle-psoc-5-community-library-dds24-psoc-4-ble-d... Have you been able to fit DDS24 and still have SW control over frequency? What is out3 in your case? DDS24 has only 2 outputs.
2. DDS24 requires input clock to operate. For high stability this clock has to be derived from XTAL in the PSoC clock distribution network. If you already have onboard 24MHz XTAL, open the Clocks subtab in Device Wide Resources panel (find it on the Project Explorer panel), and configure XTAL to be the IMO source.
P.S. The DDS-related question has been hangled in the link above.
I'm using the DDS24 component in a project. Actually I'm using two of them, and need to keep them synchronized. I use a common hw enable line and I use the load signal to program them in parallel. But if I set them to different frequencies, and then later set them to a common freq, I can't figure out how to get them synchronized, as they are at startup. I've tried DDS_Start and DDS_Init on both, but that doesn't seem to do the trick. Is there a way to re-sync them, so that the counters are identical?
p.s. I know that I can get two outputs from single DDS24, with separate phases, but I'm using that primary output for something else, and I really do need two instances.
The DDS24 component currently does not have reset input. Adding a hardware reset to the Verilog code is rather simple, what takes time is rigorous resting of the component in various conditions.
As an alternative I can suggest to use another component (DDS32), which does have a hardware reset input. Project example showing synchronization of two DDS outputs is attached. Check if DDS32 works for you first.
The DDS32 component can be set to operate in 8,16,24 or 32-bit mode, and has hardware enable/reset inputs, but no phase output. Unlike DDS24, which built entirely in PLD space, DDS32 uses UDB only. Attached is a beta version of the component, but there is no "official" release (no datasheet / demos, etc).
The demo uses QuadDecoder_SW custom component which can be found here:
Thanks. I am using many of the DDS24 features (2nd phase-shifted output, load signal, etc., so perhaps I’ll try and learn enough to add the reset for my purposes.
Thanks for creating these components, as well as the Sin8 component which I use in my project.
Attached is new version (v0.1) of the DDS24 component, now equipped with a reset input. It provided as-is, meaning that component appears to work, but it has not been tested thoroughly at various conditions. Project example showing hardware synchronization of two DDS outputs is attached.
That solves my problem perfectly! I had actually tried doing it myself today, and although I got it working, my version somehow used about 25% more UDB resources than yours does, which caused it not to fit. (It was my first attempt at both Verilog and packaging a PSOC component.) Your version seems to remained exactly the same size, and works great. Thanks so much.
p.s. A fun video of Lissajou figures made with 2xDDS24 + Sin8: https://www.dropbox.com/s/g7mujs5n7ycmrul/Lissajou.MOV?dl=0
The output looks beautiful! Where did you find the old tube? I suggest to post the video on YouTube for public display.
There are a fair number of old CRTs floating around for sale on ebay and other places. I got inspired by some other CRT-based clocks that I saw online, and decided to use the PSOC as the controller and waveform generator to drive one. I’ll put some better videos up when I get things better integrated.
Here’s one of it behaving like a clock: https://www.dropbox.com/s/ocyap5fpmsycp7o/IMG_0454.MOV?dl=0 <https://www.dropbox.com/s/ocyap5fpmsycp7o/IMG_0454.MOV?dl=0>
Thanks again for the reset capability.
Since it's implemented in UDB only, your DDS32 seems like it could be what I need for an old PSOC 3-based system that I have. Do you think it could work?
I don't have PSoC3 to test it. But both the Datapath and API are very simple, I expect only little tweaks might be needed.
Thanks. I have just tried a simplified version of your DDS32 project on a PSoC3 (device type CY8C3866LTI-068 QFN48.) It compiles/builds without errors or warnings and it does seem to work. I wasn't able get as high as 24 MHz output for an input clock frequency of 48 MHz but that might have something to do with tolerances. I'll keep investigating and if I come across anything strange and/or interesting then I'll post it here.
It is not possible to reach frequency of Clock/2 with DDS. The closer you get to 1/2 of clock, the output gets more jittery. Only way is to increase driving clock, with PSoC 5LP 80MHz is possible.
That's correct. It seems to be more like a theoretical question, as by changing the input clock, the output can get almost infinitely slow. Usually DDS important parameters are resolution and upper usable frequency. You may also refer to a similar DDS24 datasheet for more info.
One more question:
If a clock the DDS32 with 1Mhz i get minimum frequency at 0.00023Hz or at 0.001Hz?
On Wed, Jul 11, 2018, 1:50 PM jorgesilva <email@example.com>
I am using the DDS24, very nice, thank you.
Is there a particular reason why it is limited to 35MHz?
The pdf states 50.7MHz, but it throws a timing analysis error above 35.326MHz
I would like to run it as high as 75MHz if possible.
The component is build using PLD section only, so it usually slows down as design grows and other logic added up, and routing path ncreases. The max frequency also decreases as more functionality enabled in the component. As-is, 75MHz is not achievable with DDS24.
1. Check if DDS32 works for you (see #15 of this thread). It has less functionality but higher max frequency. It is independent of design, as it implemented in UDB datapath.
2. Try to add Sync component to register DDS output (or simple DFF).
3. Can post your project for review here (Build->Clean. File->Create Archive. Delete Generated source folder in zip archive.)
4. Finally, DDS24 can be spead-up by pipelining. In tests it went up to 70+MHz in basic configuration, but it takes more PLD space + need some time to "dust off".
Good day, Odissey,
Recently I am doing a project which using PWM to generate the frequencies with the range 0.01Hz, 0.10Hz, 0.20Hz, 0.50Hz, 1.0Hz, 2.0Hz, 5.0Hz, 10.0Hz, 50.0Hz and 100.0Hz and I fail to generate 0.01Hz due to the reason insufficient bit wide resolution on PWM. My question is can DDS24 generate different frequencies range and select for the respectively frequencies?
Yes, the DDS24 or DDS32 will be good replacement for PWM. To cover 0.01Hz -- 100Hz I would recommend DDS32 (post #15 above) attached to some slow clock, derived from the MASTER_CLK.
For example, starting with MASTER_CLK=24MHz, set DDS_CLK = MASTER_CLK/128.
Then lowest clock achievable will be:
24.0MHz / 128 / 2^32 = 0.0000436 Hz
that is 0.01Hz /256 accuracy!
and the highest clock
24.0MHz / 128 / 2 = 93,750 kHz
Changing the frequency output is very simple by using API:
Hi, thank you for your reply,
As the example you stated above, I have tried for it with similar slow clock you have stated above and a button input is used to trigger the frequency values which needed to set inside the DDS32 API and output the frequency to a digital output LED and I found that the frequency blinking LED is not similar to the frequency which set to the DDS32.
Is there any issue for causing this problem?
In the Basic Dialog, check setting for the input clock frequency ClockFreq, it must be exactly the frequency you providing from input clock DDS_CLK. For example, if DDS_CLK = 24MHz/128 = 187500.0 Hz, set parameter ClockFreq to 187500.0.
Please note that Sine output frequency will be DDS_OUT_FREQ / SINE_TABLE_SIZE. Are you sure the such low frequencies are needed?
If, otherwise, 0.01 Hz is required Sine frequency, then DDS32 should be set to operate faster: DDS_OUT_FREQ = SINE_TABLE_SIZE * .01Hz
Just wanted to say thanks for creating this component. Saved me a heaps of time in creating an ISO11784 tag simulator.
You are welcome. I hope that no animals have been hurt while testing the device.
Could i use your DDS24 for a project I am working on to generate square waves that run from 500Hz to 1397Hz at 8 cycles per minute?
You may find an example of both software- and hardware-timing frequency sweep generator examples in the example projects, provided along with the component. Please check the App Note, which describes both types.