Hello,
This sample code implements SmartIO's Count Up Wrap function using a Divided Clock.
The Clock component is connected to the clock of SmartIO2.
GND is connected to TR0 (rst) and VDD is connected to TR1 (en) of Count Up Wrap, but since it cannot be directly connected, it goes through LUT0 and LUT1, respectively.
DU is a Count Up Wrap function, and the counter outputs a pulse with 6 counts match of 8bit counter.
The output of DU is registered out to gpio6 with LUT6 .
2_1 is connected to VDD and P2_0 is connected to GND by external wiring.
The following waveforms can be observed after programming.
Pin_PWM_CLK (P3_6) is a clock for waveform observation with an oscilloscope.
And note that the Clock component output is divided by two.
Best regards,
Yocchi
