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Translation_Bot
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TC3XX ETH characteristics:

1. Supports 10/100/1000M Ethernet;

2. Supports MII/RMII/RGMII interfaces;

3. Supports full/half duplex working mode;

4. The maximum length of an Ethernet frame is 1522bytes;

Only TX DMA0 and RX DMA0 are used in 5.mCal.

The hardware structure diagram of ETH is shown in the following figure.

 

ReaganYang_8-1701063692660.png

 

Key API interfaces in MCAL:

  1. eth_17_gethMac_init, used to enable and reset the ETH module and initialize the Mido interface;

  2. eth_17_gethMac_provideTxBuffer, used to create the specified buffer to be sent. The input parameters include Controller, BufferId, Buffer content, and length.

  3. eth_17_getHMac_setControllerMode, sets the mode of the Ethernet controller.

  4. eth_17_gethMac_getControllerMode to get the mode of the Ethernet controller.

  5. eth_17_gethMac_setPhysAddr, set the MAC address of the controller.

  6. eth_17_gethMac_getPhysAddr to obtain the MAC address of the controller.

  7. eth_17_gethMac_writeMii, set the contents of the PHY register.

  8. eth_17_getHmac_readMii, reads the contents of the PHY register.

  9. eth_17_getHMac_transmit, Ethernet data transmission.

  10. eth_17_getHMac_receive, Ethernet data reception.

  11. eth_17_gethMac_Tx, callback function for Ethernet data transmission.

MCA configuration:

The first step is to configure the clock reference, as shown in the following figure.

 

ReaganYang_10-1701063764957.png

 

The second step is to configure the controller, including speed, operating mode, MCA address, buffer level, MDIO, etc., as shown in the following figure.

 

ReaganYang_11-1701063784579.png

 

The third step is to configure the transmission and interface interfaces, enable RGMII read and write operations, and configure the form of data reception.

 

ReaganYang_12-1701063814848.png

 

The fourth step is to configure the port hardware as the reset type. All input pins used for the ETH drive must be configured as port_pin_rgmii_driver, PORT_RGMII_INPUT, as shown in the following figure.

 

ReaganYang_13-1701063837193.png

The fifth step is to enable the transmission and reception of DMA to be interrupted.

 

ReaganYang_14-1701063854821.png

Step 6. Compile the configured generated.h and.c files into HighTec or TASKING.

 

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E4%BE%8B%E7%A8%8B/Aurix-TC3xx-ETH-Demo/td-p/647552

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Translation_Bot
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Manually like and look forward to more sharing 👍 😁

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/%E4%BE%8B%E7%A8%8B/Aurix-TC3xx-ETH-Demo/m-p/649102

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