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Audio Sinewave Generator using a CY8CKIT-059, CY8CKIT-030, CY8CKIT-050 or CY8CKIT-062-BLE

Level 9
Level 9
500 solutions authored 1000 replies posted 750 replies posted

UPDATE: 11.07.2021 in BLUE.

I've created a relatively simple sinewave generator for audio testing applications.  It uses a CY8CKIT-059, CY8CKIT-030, CY8CKIT-050 or CY8CKIT-062-BLE.

The project supports the following audio frequencies (in Hz):

10 100 1000 10000  
20 200 2000 20000  
30 300 3003  
40 400 4000  
50 500 5000  
60 600 6024  
70 700 7042  
80 800 8000  
 90 900  9009  

For the CY8CKIT-059 I'm using the USB IMO clocking which is suppose to be +/- 0.25% accuracy. 

For the CY8CKIT-030, I use the on-board 24MHz crystal for even better frequency accuracy (+/- 0.02%). 

I've used this device to test some audio equipment for frequency response such as tri-powered speakers and mixers with equalization features.

It also has the following features:

  • A single-digit 7-segment display (for the most significant character).
  • 4 LEDs for the least significant 0s characters.
  • It uses the PSoC low-pass-filter (my custom component) to help to reduce any digital harmonics created by the WaveDAC8 component.
  • Two switches for Up/Down frequency selection.
  • Uses the micro USB connector for USB power input so that the KitProg board can be removed.
  • I'm using a 1/8" audio connector for unbalanced capacitor-coupled audio output.  You can use other connectors such as RCA phono, 1/4", XLR, etc.
  • Each waveform is maximized (and calculated) to reduce step transitions up to the 1Msps allowed by the WaveDAC8 component.  This allows for the smoothest sinewave with the least amount of harmonics.




You can use fixed resistors to limit the drive the segments of the 7-segment display.  I chose to use the SIO outputs (Port 12) with voltage regulation.  I used a 30 ohm resistor on the common line of the segments.  I then monitor the voltage across this resistor.  The voltage represents the combined current flowing through the segments being turned on.

The target current per segment in this design is 4mA.   There for the digit '8', all 7 segments are lit and should have a combined current of 7 x 4mA  = 28mA (= 0.840V / 30 ohms).  Therefore I can increase the voltage of VDAC8_LED_vref until I get 0.840V across this resistor.  For the digit '1' (2 segments), I target 2 x 4mA = 8mA => 8mA * 30 = 0.240V.

Why did I do this?  Besides reducing external components (8 resistors to 1 resistor), because I could!  This technique has its limitations but is useful as a learning exercise.

You can use this to learn how to use the SIO port pins in a voltage regulation mode as well as using the ADC to create a feedback control loop.

Here are a some of pics of the assembled projects:

20,000 Hz20,000 Hz800 Hz800 Hz

UPDATE:  10/27/2021

I've uploaded two projects.  One for the 059 kit and the other for the 030 kit.

UPDATE: 11/7/2021

The CY8CKIT-050 project uses the included LCD display.

For the CY8CKIT-030, I use the included LCD display.

The CY8CKIT-062-BLE uses the included EINK display and Capsense Slider and Buttons for minimal external support.

Project feature additions:

  • Pressing BOTH switches simultaneously forces it to the "home" frequency (1KHz).


"Engineering is an Art. The Art of Compromise."
6 Replies
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted


It is useful idea to include a LPF between VDAC and Opamp buffer!



I'm curious, would a DFB between the VDAC and Opamp work better to fine-tune the corner frequency more accurately?  Would it be better to use the DFB as a notch filter?

"Engineering is an Art. The Art of Compromise."


I am not sure how to squeeze DFB between analog parts. I like your approach of placing analog LPF with cutoff 75-200kHz between VDAC and Opamp. The reason is PSoC5's VDAC8 has a glitch upon bit flipping ...01111<->...10000 (16 per scale), which particularly pronounced at higher update frequencies (>0.5MHz). For example, PSoC4 VDAC doesn't show this phenomenon (at least it is not that pronounced). Pacing analog LPF after VDAC can eliminate such effect.

Fig. 2. Example of VDAC8 glitch upon bit flipping (spikes on the ramp profile)




I am not sure how to squeeze DFB between analog parts.

Duh.  Makes sense.  

I tried to reproduce your results for the glitch with the following specs:

  • WaveDAC8
  • 0 to 1.020V unbuffered
  • Sample Rate: 1000Ksps (maximum allowed
  • Internal clock
  • Wave type: Sawtooth
  • Samples: 64

I get a 15.56Khz frequency like your wave.

Here's my scope pic.  No glitches.


Can you share your project that produces the glitches?

"Engineering is an Art. The Art of Compromise."


The VDAC should be buffered by opamp to see the glitches. Without Opamp the output gets smoothed out by scope probe capacitance. I would use 256 samples/period to guarantee that the bit flips ...01111 - ...10000 are not missed.

I havn't supplied the project - today is busy day, will do on weekend. 



I set up my WaveDAC with 0 to 1.02V buffered with 64 samples/period and sending it out P0.0 to get the best lowest output impedance.


No glitches.

However, if I use 256 samples/period I start getting glitches.  Yes there appears to be a non-linearity at the nibble crossover point.

I also noticed the following:

Your ramp frequency on your plot is 15.56KHz.  With 256 samples, this  requires an external clock of (15.56K * 256) ~ 4 MHz.  This input frequency is above the maximum sample rate for 0 to 1.02V range.  Given what appears to be a nibble crossover issue, exceeding the max sample rate is probably exacerbating the issue making the glitches larger.

"Engineering is an Art. The Art of Compromise."