Tracking skew can be defined as the deviation of the output of the PLL from its input.

We can expect the feedback signal to be stable as any variations there itself can cause instability with the locking and have the PLL working in Acquisition and tracking mode which are the two states of a PLL: phase-locked or acquiring lock. Any larger change to the frequency and phase to the Reference or Feedback is going to make the clock lose its lock and relock to the new frequency and phase. Cypress usually does not define and measure the tracking skew for the devices and provide as a value. It should be noted that PLLs are normally capable of tracking long-term jitter. PLLs, by design, are incapable of tracking cycle-to-cycle jitter, because the PLL response time is typically slow. When the modulation occurs at a rate and level that is too difficult for a PLL to track, the PLL may give a “best-effort” tracking which is referred to as tracking skew.     

Tracking is synonymous with the locked condition and simply describes the extent to which the loop can follow variations in the input clock frequency. PLLs operate on the phase of signals and therefore are susceptible to changes in the clock edges on the inputs. The transient response of a PLL is generally a very complex, non-linear process. In general terms, the PLL will follow the presence of a slowly occurring signal at the input and does not react to rapidly occurring transitions (frequencies outside of the PLL’s loop bandwidth).     

So with the Tracking skew, cascaded PLLs can have an adverse effect on the amount of skew exhibited. Modulations and excessive input noise that are sometimes created by jitter peaking, can lead a phase-locked loop into a condition of instability that results in less than optimal output conditions.

The jitter transfer characteristic is that of second order low-pass filter with the -3dB point at approximately 1MHz-3MHz depending on its internal configuration (also called close loop bandwidth). This means that if the jitter frequency is less than loop bandwidth, it will pass through the PLL and appear on all outputs.

Jitter transfer characteristics of clock buffers actually peaks at 1MHz where the jitter increases and then rolls down with 20-dB/decade attenuation.

Time Unit (tU) is adjustment phase granularity. In RoboClock family, the CY7B993V and CY7B994V have it ranging from 0.625ns to 1.25ns. The CY7B991 and CY7B992 have it ranging from 0.7ns to 1.5ns. The selectable skew is in discrete increments of time unit (tU) where more options are available in CY7B993V and CY7B994V devices. As mentioned in the datasheets, the value of a tU is determined by the FS setting and nominal output frequency (fNOM) with the equation to be used to determine the tU value given as tU = 1/(fNOM*N). Here, FNOM is the VCO operating range and N is the multiplication factor whose value is determined by the Frequency Select and N value table in the respective datasheets.

The CyClocksRT uses a proprietary algorithm to optimize the charge pump value. The table 9 in the datasheet will give you guaranteed PLL stability, but will not necessarily be the optimum solution. It is recommended to refer the CyClocksRT charge pump value for critical configurations.

The datasheet values are set to cover a wide range of possible P values, while CyClocksRT knows exactly which P value you will be using.

The datasheet table chooses the lowest charge pump value acceptable for a specific range of P values; the lowest value will give you the most stability margin.

CyClocksRT goes from the highest charge pump setting and calculates the loop bandwidth, if the phase detector frequency, which is equal to VCO/P, is 5 times greater than the calculated bandwidth it will stop searching. Otherwise it will go to the next lower charge pump setting and go through the calculation again.

This is why you see values from software different from the table 9 in the datasheet. 

The charge pump values that you get from the table 9 in the datasheet are valid entries, and will give you a stable clock output.

The values generated out of both CyClocksRT and table 9 will guarantee stability. There is a range in which the charge pump can be set and the values from table 9 are usually around the center of that stability region. CyClocksRT will try to get to the optimum area of the stability region.     

So it is strongly recommended to use CyClocksRT for jedec file configuration that should be used for programming the device.

As can be seen VOH and VOL specifications for programmable clocks are not specified. In the Electrical Characteristics table of CY22393, for example, lists IOH with a condition of VOH=(L)VDD-0.5, (L)VDD = 3.3V. For this condition when VOH = 2.8V (3.3V-0.5V), Cypress guarantees that there will be at least 12mA of current being driven from our part. The 12mA is a minimum specification that the designers need to design to. It is a minimum value chosen by design and marketing that Cypress can guarantee the part will drive. Most likely there will not be a case where the driver will only source/sink 12mA.    

The outputs are tested by setting the clock output voltage to either GND (IOL) or VCC (IOH) and using external equipment to sweep the voltage from 0 to VCC and measure the current at each voltage step. This produces I-V curves where Cypress looks to see what the minimum current is at the specified voltage. In this case 2.8V has a minimum of 12mA under worst case conditions, but normally is around 24mA.     

Cypress does not specify the other way around specifying a current and state the voltage level.

Whenever you generate a jedec file from CyClocks for CY2292F, it adds in date code information on the last line of the file. This causes the differences in checksums for the same configuration. So generating a JEDEC file from the software will give you a different JEDEC checksum due to the last line in the JEDEC file that contains time and date information. All of the other lines above in the JEDEC should match though. The bits contained in rows 100-140 do not configure the device. It is date code information which is not necessary and can be ignored. If you compare all of the other lines in the JEDEC file they will be the same for the older devices, the factory programmed devices, and the field programmed devices.     

Drive Strength settings changes affects the edge rate. It is used to reduce the EMI. Changing the bits as mentioned in the respective datasheets, the DC level is shifted percent wise of the nominal as per the bit settings mentioned. However, reducing the drive strength to reduce EMI, in turn can increase the jitter due to the slower edge rates.     

Conversely, increasing drive strength gives faster edge rates, more EMI and less Jitter.     

This applies to programmable clock whose drive strength can be configured in Advanced mode of CyClocksRT software, that in turn change the bit settings mentioned in the datasheets, like CY22050, CY22150, CY22381, CY22392, CY22393/4/5 and CY22801.     

The clipped sine wave is not a problem. If you turn off all of the load capacitors in the programmable clock devices, this will reduce the capacitance load on the XIN Pin to 12pF for the CY22392, CY22393/4/5, CY22381 and 15.6pF for CY22050, CY22150, CY22801 that can be programmed using CyClocksRT. You will then need a clipped sinewave of +/- 1 Volt peak to peak on the input side or XIN side of an AC coupling capacitor connected back to the output of the TCXO.

     

There are no specific TCXO recommendations, but from an application point of view, Cypress clock generators and programming software are set up to handle a driven external reference. The easiest recommendation is to simply purchase a low cost 3 by 5 mm TCXO and drive this into your chosen part as the clock reference.

For the external reference, as long as the input reference signal goes through [(VDD/2) +/- 1V)], it should be fine as the phase detector compares the Reference and Feedback signal at the rising edges at VDD/2 level. So only going through VDD/2 should be sufficient, the added “+/-1V” on top of it is for the noise margin.

The ppm values specified in datasheet is ppm with no spread.

Here is what the data says for each component of PPM in non-spread mode:

1. Frequency Stability at Room Temp (25C, 3.3V) +/- 25ppm
2. Frequency Stability Over Temp Range (-20C to 70C, 3.3V) +/- 25ppm
3. Frequency Stability Over Voltage Range (3.0 to 3.6V) +/- 12ppm
4. Frequency Stability Over Output Freq Range (10 - 166MHz) Determined from CyberClocks
5. Aging is +/- 5ppm @25C, First year

     

The 4th item is the PPM due to the P & Q that CyberClocks will select for the customer's desired output frequency. This error if any will be a calculated error based upon the one’s exact frequency and application. This will be in addition to the above stated crystal and circuit variations.     

Since the P and Q values affect the total operation of the internal PLL there is no blanket error budget for the calculated error. One should simply input their frequency into CyberClocks Online and add that error if any to the total PPM budget.

     

An example calculation to clear things up is as follows:    

The CY25701 may be 25 PPM low at room temperature and another 25PPM low at -20C. For this example, the temperature and room tolerance accuracy error would be a total of -50ppm at 3.3 volts and -20C.    

If you add the stability over voltage and use as an example -12ppm at 3.0V this would set the PPM error at -62ppm low not including aging or the calculated error if any.     

Next the calculated error for the exact application may be -8ppm.    

Therefore the total error in this example not counting aging would be -70ppm low at 3.0V,-20C.

Ferrite beads are used in power supply filtering as they reduce the injection of clock noise into the main VDD supply. At the same time they also increase ripple in Cypress clock devices. It would also filter the necessary signal current and hence ferrite bead is usually not recommended to be used. When a ferrite bead is added to the Vdd path, it increases the Vdd path inductance. This is good for EMI, but it makes it that much more important that very good decoupling be provided between the ferrite and the chip.     

As everyone is aware, Ferrite beads offer a level of filtering to produce the absolute best quality in signals. It is very difficult to determine which ferrite bead will perform the best based on the manufacturers specifications. By using data from a test environment, a bead that will filter the noise can be selected. We have detailed analysis in Chapter 5 of our Perfect Timing II book, available on our website at: http://www.cypress.com/?rID=98 that gives general as well as specific guidelines that may or may not be given in the device datasheets. Although it is difficult to select which bead will perform best, the analysis and recommendations presented in this chapter provides the necessary guideline information.

When quality of the voltage supply degrades, so does signal integrity. Noise in the supply will affect jitter and skew in clock buffers. Essentially, one may want to use bypass capacitors (usually of 0.1 uF) attached to each pair of power and ground pins placing the bypass capacitor as close to the device pins as possible.     

Check the Perfect Timing II book that also discusses Power Supply Filtering.