Clocks Forum Discussions

Drive Strength settings changes affects the edge rate. It is used to reduce the EMI. Changing the bits as mentioned in the respective datasheets, the DC level is shifted percent wise of the nominal as per the bit settings mentioned. However, reducing the drive strength to reduce EMI, in turn can increase the jitter due to the slower edge rates.     

Conversely, increasing drive strength gives faster edge rates, more EMI and less Jitter.     

This applies to programmable clock whose drive strength can be configured in Advanced mode of CyClocksRT software, that in turn change the bit settings mentioned in the datasheets, like CY22050, CY22150, CY22381, CY22392, CY22393/4/5 and CY22801.     

The clipped sine wave is not a problem. If you turn off all of the load capacitors in the programmable clock devices, this will reduce the capacitance load on the XIN Pin to 12pF for the CY22392, CY22393/4/5, CY22381 and 15.6pF for CY22050, CY22150, CY22801 that can be programmed using CyClocksRT. You will then need a clipped sinewave of +/- 1 Volt peak to peak on the input side or XIN side of an AC coupling capacitor connected back to the output of the TCXO.

     

There are no specific TCXO recommendations, but from an application point of view, Cypress clock generators and programming software are set up to handle a driven external reference. The easiest recommendation is to simply purchase a low cost 3 by 5 mm TCXO and drive this into your chosen part as the clock reference.

For the external reference, as long as the input reference signal goes through [(VDD/2) +/- 1V)], it should be fine as the phase detector compares the Reference and Feedback signal at the rising edges at VDD/2 level. So only going through VDD/2 should be sufficient, the added “+/-1V” on top of it is for the noise margin.

The ppm values specified in datasheet is ppm with no spread.

Here is what the data says for each component of PPM in non-spread mode:

1. Frequency Stability at Room Temp (25C, 3.3V) +/- 25ppm
2. Frequency Stability Over Temp Range (-20C to 70C, 3.3V) +/- 25ppm
3. Frequency Stability Over Voltage Range (3.0 to 3.6V) +/- 12ppm
4. Frequency Stability Over Output Freq Range (10 - 166MHz) Determined from CyberClocks
5. Aging is +/- 5ppm @25C, First year

     

The 4th item is the PPM due to the P & Q that CyberClocks will select for the customer's desired output frequency. This error if any will be a calculated error based upon the one’s exact frequency and application. This will be in addition to the above stated crystal and circuit variations.     

Since the P and Q values affect the total operation of the internal PLL there is no blanket error budget for the calculated error. One should simply input their frequency into CyberClocks Online and add that error if any to the total PPM budget.

     

An example calculation to clear things up is as follows:    

The CY25701 may be 25 PPM low at room temperature and another 25PPM low at -20C. For this example, the temperature and room tolerance accuracy error would be a total of -50ppm at 3.3 volts and -20C.    

If you add the stability over voltage and use as an example -12ppm at 3.0V this would set the PPM error at -62ppm low not including aging or the calculated error if any.     

Next the calculated error for the exact application may be -8ppm.    

Therefore the total error in this example not counting aging would be -70ppm low at 3.0V,-20C.

Ferrite beads are used in power supply filtering as they reduce the injection of clock noise into the main VDD supply. At the same time they also increase ripple in Cypress clock devices. It would also filter the necessary signal current and hence ferrite bead is usually not recommended to be used. When a ferrite bead is added to the Vdd path, it increases the Vdd path inductance. This is good for EMI, but it makes it that much more important that very good decoupling be provided between the ferrite and the chip.     

As everyone is aware, Ferrite beads offer a level of filtering to produce the absolute best quality in signals. It is very difficult to determine which ferrite bead will perform the best based on the manufacturers specifications. By using data from a test environment, a bead that will filter the noise can be selected. We have detailed analysis in Chapter 5 of our Perfect Timing II book, available on our website at: http://www.cypress.com/?rID=98 that gives general as well as specific guidelines that may or may not be given in the device datasheets. Although it is difficult to select which bead will perform best, the analysis and recommendations presented in this chapter provides the necessary guideline information.

When quality of the voltage supply degrades, so does signal integrity. Noise in the supply will affect jitter and skew in clock buffers. Essentially, one may want to use bypass capacitors (usually of 0.1 uF) attached to each pair of power and ground pins placing the bypass capacitor as close to the device pins as possible.     

Check the Perfect Timing II book that also discusses Power Supply Filtering.     

When you want fair comparisons made while looking at the cycle to cycle jitter numbers, there are few points to remember as follows:

As specified in JESD65B spec, cycle to cycle jitter requires at least 1000 samples to be taken. So while comparing one should see if the measurements are made with the same number of samples. More samples will have more data resulting in bigger jitter value and less samples have less data resulting in lesser jitter value.

Also, JESD65B spec says that the cycle to cycle jitter should be mentioned as a peak value. So if any datasheet mentions that to be peak to peak measured, the actual cycle to cycle jitter peak value becomes half.

For fullproof comparison, request samples and measure with the same equipment and conditions.

 Cycle to Cycle type of jitter has a random (i.e. Gaussian) distribution, the tails of this distribution are unbounded, and therefore the "worst-case" jitter you'll see from any device will always increase the longer you measure it. This is just a simple fact of nature, and is common from all manufactured parts, at Cypress as well as other companies. This may give you an unsettled feeling at first, but keep in mind that although the worst-case jitter you measure with time will always increase, the probability of getting that jitter is always decreasing, so in the end, you should stop measuring jitter because the chance of seeing a larger jitter number is so small you'll have to wait days, weeks, years, to see an increase in the last measured "worst-case" jitter number.

 The typical peak-peak period jitter value is completely determined by the configuration of the device. In general, jitter can be reduced by using the least number of outputs and PLL's, or using smaller Q values. We can optimize the parameters P and Q. You can calculate the P and Q values using the Cyberclocks software, available on our website. The jitter varies with the different configurations. There are certain factors that help in minimizing jitter for a particular configuration. 

Your jitter will be reduced when you minimize the number of PLL's running on the die. The worst case jitter depends on how many outputs and PLL's are running as well as what combinations of frequencies are running on the chip.

Keeping VCO frequencies high as possible will always give you better jitter performance. The way to minimize jitter is to run the minimum number of outputs and PLL's. Also having clean multiples of the input frequency will help reduce jitter in some cases as well.

Lower frequencies generally have higher long term jitter because there is a larger chance of variation with the longer period lengths. A 1us period for a 1MHz signal with 1% of jitter can vary up to 10ns, a 10ns period for a 100MHz signal with 1% of jitter can vary up to 100ps.

So with a lower frequency, either your VCO is running slower which increases jitter, or you are using a larger divider value which can also increase the jitter. The larger divider value can increase jitter because you have that much more logic and circuitry to go through, and each gate can add a little more variation which will accumulate and show up in the final output frequency.

So again, in cases where reducing jitter is of paramount importance, it is recommended running fewer PLLs in case of multi-PLL devices.

 If you are finding any difficulties getting crystal with the specifications in the CY24293, look at the Abracon ABLS series that meets the specs. Attached is the datasheet.

For the CY22050 and CY22150, the AVDD powers the PLL, VDD powers the crystal oscillator and CLK5 and CLK6, and VDDL powers LCLK1-LCLK4. You should bring up both VDD and AVDD with a smooth monotonic ramp, but VDDL can be powered up or down at any time. Powering it down while still powering AVDD and VDD is not a problem.

During power up, important events takes place where the start up registers are loaded to put the part in a start-up condition. If the power ramp is not monotonic, the start up conditions will be lost and the device may come in an unknown state and not behave as expected. So it is recommended that the power ramp specification be applied as specified in the datasheets.

Always look and go for Spread Aware Clock Buffers for signal distribution when you want Spread Spectrum signal to pass as they have larger close loop bandwidth. Normal Clock Buffers will filter the spread spectrum signal. Cypress has such buffers with an “S” in the part number. Examples are CY23S02, CY23S05, CY23S08 and CY23S09 with 2, 5, 8 and 9 outputs respectively.

Check Clocks and Buffers Product Selector Guide for detailed part numbers at (Devices are listed on page 11):

http://www.cypress.com/?rID=34778