I am using the CY26049-20 as a synchronized clock filtering circuit with with fall back
So I hope to apply a 25MHz ICLK and obtain a 100 MHz phase locked output, and using a 25MHz XTAL input
Obviously I am having some difficulty getting it to function properly
I was wondering if there are any application, layout guide, notes or any data at beyond the basic datasheet for this part. I am using the the -20 par but the only datasheet I can find is the -36 version. so even getting the -20 or generic data sheet would be helpful. Too bad there is no Eval board for this part 🙂
I just programmed CY29421FLXI-ND using the clockwizard. When look at each output (single ended) on the scope, i see both clk+ and clk- in sync. Basically clock complement is missing. was there any setting in clockwizard to set the second output as complement of the 1st output one that i missed?
Does CY29421FLXI-ND support VCXO function? i notice it lacks VC pin.
Do I need to disabled this function in clockwizard tool for CY29421FLXI-ND?
What are the conditions required by Infineon in term of MOQ for having a factory configured CY2545QI ?
Also, what would be the extra lead time du to this configuration step ?
For instance, the configuration would be :
I presume no extra information is required. Am I right ?
Thank you in advance for your support,
I am planning to use CY29421FLXI-ND on 3.3V rail, but looks like I2C port is only spec at 2.5V max. is this correct?
Can i pull up I2C signals to 3.3V for this Clock? is it 3.3V tolerant?
I need help on how to generate programming file for CY29421FLXI-ND to give to the programming house.
we need to set the following options:
I am using CY2305 with the configuration shown in the schematic below.
I measured the waveform of CLK1. It has a lot of jitter. (Approximately 2ns)
According to the data sheet, Cycle-to-cycle jitter is 200ps(max), but there is no Period jitter spec. Is this waveform normal? If yes, what can I do to reduce jitter?
I measured CLK1, but the waveform (jitter) is the same for the other output pins. It does not change depending on the load of the opposite device. Jitter tends to increase at high temperatures.
We use CY2305SXI-1H on a design where we are receiving back for several customer defect reports during start-up at low temperature (lower than 10°C). After deep investigation on the design, we have probably found a defect root cause which is clock output interruption even after the stabilization of 1 ms after a clock shift on the fly.
As you will see in the scope snapshot hereunder :
-Yellow signal is the end of the 1 ms delay (go low when timer is elapsed) ;
- Cyan signal is the clock input (switching from 8,33 MHz to 100 MHz) at the beginning of the 1ms delay ;
- Magenta is one clock output. As we can seen we observe multiple clock interruptions even after 1ms of stabilization during power ON at low ambient temperature (lower than 10°C). Important to notice that this anomaly is not observable on all devices (probably less than 5 % but not fully characterized as per today).
Did you receive such equivalent user's feedback ?
Could you help us to investigate on which factor it could be linked ? Could it be linked to manufacturing issues linked to some component ?
Thanks in advance for your technical support.
Stephan COLLEShow Less