Clocks Forum Discussions

Tips to minimize output-output skew are as follows:

1. Keep same length transmission lines at output.

2. Allow only one frequency output simultaneously.

3. Use same Vdd on all output buffers.

4. Terminate outputs in same way; use sufficient bypass capacitors.

5. For devices in parallel, feed inputs same ref clock in most symmetrical way possible.

6. Route outputs in most symmetrical way possible.

Making a choice to go for ZDB (Zero Delay Buffer) or NZDB (Non-Zero Delay Buffer) is fairly dependent on your application requirements.

With ZDB, we have a PLL inside that gives zero delay between input and output. This filters jitter present at the reference and has less jitter at the output in ps (Jitter can be minimal but never zero).

With NZDB, there is no PLL inside; it is just a Fan-Out buffer. This is not going to filter any jitter at the input and has a propagation delay.

So while making a choice, between in a ZDB and NZDB,

You select a ZDB if your source has a bad jitter that needs filtering and you require a Zero Delay between input and Output. You will also get variants with divider options to have frequency multiplications and divisions and also can adjust skew with ZDBs.

You select a NZDB, if you have a very clean source and need just fanout of the source with less additive jitter. However, your application should be fine with the propagation delay, the NZDB will have. You will have different options to match different signaling standards here.

AVCMOS name/design came in from one of the companies Cypress acquired, IMI. It is another name for variable output impedance (VOI), or sometimes called variable slew rate (VSR). It is a type of output buffer that has a strong drive current from the beginning of a switch (ie. rise or fall time) to about the mid-point of the switch. At about mid-point, some of the legs of the transistors shut off so that the drive current is reduced, and the resulting transition from mid-point of the switch to the final settling value is smooth (i.e. little overshoot/undershoot). This way, higher frequencies can be achieved without as much overshoot/undershoot. It's called "variable impedance" because the impedance changed depending on whether you're looking at the start of the rise/fall time or the end. Actually, "variable slew rate" is perhaps a more accurate description.     

Check the KnowledgeBase Article Titled: AVCMOS Outputs of CY2CC810 Explained at: http://www.cypress.com/?id=4&rID=39987

The output impedance of Cypress Zero Delay Buffers is between 20-30 ohm, unless otherwise specified in the datasheets. So its recommended to use a 20-30 ohm series resistor to match a 50 ohm transmission line. Since the output impedance for the ZDBs is between 20-30 ohm, it is recommended to start with (X-28) Ohms series termination placed as close as possible to each output pin (where X is the transmission line impedance you connect to), thus assuming a 28 Ohms output impedance initially. So if you connect the output to 50 Ohms, then 50-28=22 Ohms series termination will be required for impedance matching.

Tracking skew can be defined as the deviation of the output of the PLL from its input.

We can expect the feedback signal to be stable as any variations there itself can cause instability with the locking and have the PLL working in Acquisition and tracking mode which are the two states of a PLL: phase-locked or acquiring lock. Any larger change to the frequency and phase to the Reference or Feedback is going to make the clock lose its lock and relock to the new frequency and phase. Cypress usually does not define and measure the tracking skew for the devices and provide as a value. It should be noted that PLLs are normally capable of tracking long-term jitter. PLLs, by design, are incapable of tracking cycle-to-cycle jitter, because the PLL response time is typically slow. When the modulation occurs at a rate and level that is too difficult for a PLL to track, the PLL may give a “best-effort” tracking which is referred to as tracking skew.     

Tracking is synonymous with the locked condition and simply describes the extent to which the loop can follow variations in the input clock frequency. PLLs operate on the phase of signals and therefore are susceptible to changes in the clock edges on the inputs. The transient response of a PLL is generally a very complex, non-linear process. In general terms, the PLL will follow the presence of a slowly occurring signal at the input and does not react to rapidly occurring transitions (frequencies outside of the PLL’s loop bandwidth).     

So with the Tracking skew, cascaded PLLs can have an adverse effect on the amount of skew exhibited. Modulations and excessive input noise that are sometimes created by jitter peaking, can lead a phase-locked loop into a condition of instability that results in less than optimal output conditions.

The jitter transfer characteristic is that of second order low-pass filter with the -3dB point at approximately 1MHz-3MHz depending on its internal configuration (also called close loop bandwidth). This means that if the jitter frequency is less than loop bandwidth, it will pass through the PLL and appear on all outputs.

Jitter transfer characteristics of clock buffers actually peaks at 1MHz where the jitter increases and then rolls down with 20-dB/decade attenuation.

Time Unit (tU) is adjustment phase granularity. In RoboClock family, the CY7B993V and CY7B994V have it ranging from 0.625ns to 1.25ns. The CY7B991 and CY7B992 have it ranging from 0.7ns to 1.5ns. The selectable skew is in discrete increments of time unit (tU) where more options are available in CY7B993V and CY7B994V devices. As mentioned in the datasheets, the value of a tU is determined by the FS setting and nominal output frequency (fNOM) with the equation to be used to determine the tU value given as tU = 1/(fNOM*N). Here, FNOM is the VCO operating range and N is the multiplication factor whose value is determined by the Frequency Select and N value table in the respective datasheets.

The CyClocksRT uses a proprietary algorithm to optimize the charge pump value. The table 9 in the datasheet will give you guaranteed PLL stability, but will not necessarily be the optimum solution. It is recommended to refer the CyClocksRT charge pump value for critical configurations.

The datasheet values are set to cover a wide range of possible P values, while CyClocksRT knows exactly which P value you will be using.

The datasheet table chooses the lowest charge pump value acceptable for a specific range of P values; the lowest value will give you the most stability margin.

CyClocksRT goes from the highest charge pump setting and calculates the loop bandwidth, if the phase detector frequency, which is equal to VCO/P, is 5 times greater than the calculated bandwidth it will stop searching. Otherwise it will go to the next lower charge pump setting and go through the calculation again.

This is why you see values from software different from the table 9 in the datasheet. 

The charge pump values that you get from the table 9 in the datasheet are valid entries, and will give you a stable clock output.

The values generated out of both CyClocksRT and table 9 will guarantee stability. There is a range in which the charge pump can be set and the values from table 9 are usually around the center of that stability region. CyClocksRT will try to get to the optimum area of the stability region.     

So it is strongly recommended to use CyClocksRT for jedec file configuration that should be used for programming the device.

As can be seen VOH and VOL specifications for programmable clocks are not specified. In the Electrical Characteristics table of CY22393, for example, lists IOH with a condition of VOH=(L)VDD-0.5, (L)VDD = 3.3V. For this condition when VOH = 2.8V (3.3V-0.5V), Cypress guarantees that there will be at least 12mA of current being driven from our part. The 12mA is a minimum specification that the designers need to design to. It is a minimum value chosen by design and marketing that Cypress can guarantee the part will drive. Most likely there will not be a case where the driver will only source/sink 12mA.    

The outputs are tested by setting the clock output voltage to either GND (IOL) or VCC (IOH) and using external equipment to sweep the voltage from 0 to VCC and measure the current at each voltage step. This produces I-V curves where Cypress looks to see what the minimum current is at the specified voltage. In this case 2.8V has a minimum of 12mA under worst case conditions, but normally is around 24mA.     

Cypress does not specify the other way around specifying a current and state the voltage level.

Whenever you generate a jedec file from CyClocks for CY2292F, it adds in date code information on the last line of the file. This causes the differences in checksums for the same configuration. So generating a JEDEC file from the software will give you a different JEDEC checksum due to the last line in the JEDEC file that contains time and date information. All of the other lines above in the JEDEC should match though. The bits contained in rows 100-140 do not configure the device. It is date code information which is not necessary and can be ignored. If you compare all of the other lines in the JEDEC file they will be the same for the older devices, the factory programmed devices, and the field programmed devices.