Clocks Forum Discussions

If you configure a programmable device with 0 PPM error and your reference configured has some ppm error to the input frequency, the error at the input reference comes out as the same error for the output.

Many of you may think of going beyond the datasheet maximum specification of Capacitive Loading.     

Generally it is possible to drive two loads from one pin; however, it is good to be cautious.

1. With Increased loading, two loads will double the capacitance loading. Maximum loading is 15pF specified in datasheets. The total device loading becomes ~30pF, which is enough to noticeably affect the edge rate.

2. Signal integrity: With two loads, layout is important. If the two loads are very close together, then it's possible to have one trace which then branches very close to the loads. However, this is not common. More commonly it is recommended branching very close to the output of the programmable clock. Then have a series resistor for each branch, located close to the branch. The resistor values will be different than when terminating a single load. Simulations are always recommended.

3. Total loading for the chip: Double loading every output on a chip has a cumulative effect on the chip and is generally discouraged. It's good if the double load is only on a single output. It's best if the other outputs are not used. If they are used, especially for different frequencies, then the heavy loading on this output may increase jitter in the other outputs.     

During power up, important events takes place where the start up registers are loaded to put the part in a start-up condition. If the power ramp is not monotonic, the startup conditions will be lost and the device may come in an unknown state and not behave as expected.     

It is strictly recommended that the power ramp be applied as specified in the respective datasheets.

There are internal weak pull-down for all the outputs. You do not need to provide pull-downs, however if you would like to provide pull downs, 5K or 10K is fine. The lower the resistor value, the strong it will pull.     

In cases where the input frequency drops below about 2 MHz, the PLL powers down and the outputs are tri-stated. In this case, the outputs are pulled low by these resistors to provide a known state.

Any unused outputs should not be connected to anything for non-PLL based buffers like CY2304NZ (NZDB), CY2CC910, CY2DL1510 (HPB) for example. For the non-PLL based buffers, unused outputs can be left floating.

 AN69091 discusses the Edge Align feature in Cypress’s programmable clock family, CY254xx and MoBL® clocks. Today’s technology products operate at GHz frequency; therefore need complex clock-tree architecture. This need requires clock skew in the system. To address such applications, Cypress has added the Edge Align feature in CY254xx and MoBL clock family.

http://www.cypress.com/?rID=50769

FleXO™ is a family of low phase noise clock generators and oscillators, consisting of both fixed frequency devices and programmable devices and with phase jitter as low as 1pS.

Have a look at the video and Application note which talks about configuring and programming of Flexo Devices.

http://www.cypress.com/?rID=45566

Thanks

Puru

 Have a look at this video and application note for Understanding  of Zero Delay Buffers and its different Applications.

http://www.cypress.com/?rID=12622

Thanks

Puru

High Performance Buffers CY2DP1502, CY2DP1504 and CY2DP1510 now support HCSL as well at the inputs. Accordingly, Cypress updated respective datasheets supporting differential input clock types to include HCSL in Features, Pin Definitions, and DC specs table sections of the datasheet.     

Jitter in programmable clocks is dependent upon the configuration for your application that is determined by the frequencies selected for the outputs with respect to the reference.     

A higher VCO frequency will always provide you better jitter performance that should be kept in mind always when we configure our programmable clocks. Lower frequencies generally have higher long term jitter because there is a larger chance of variation with the longer period lengths. A 1us period for a 1MHz signal with 1% of jitter can vary up to 10ns, a 10ns period for a 100MHz signal with 1% of jitter can vary up to 100ps.

With a lower frequency, if your VCO is running slower, it increases jitter, or if you are using a larger divider value, it also increases the jitter. The larger divider value can increase jitter because you have that much more logic and circuitry to go through, and each gate can add a little more variation which will accumulate and show up in the final output frequency.

The typical peak-peak period jitter value totally depends on the configuration of the device, number of outputs in use, output loading. Same frequency on all outputs and equal loading will have smaller jitter numbers. Jitter can be lowered by using the least number of outputs. Another parameter is the Q value. Using smaller Q values will also help decrease the peak-peak jitter. Different frequency combinations will yield different P and Q values, and you generally want the lowest P and Q values possible.