Clocks Forum Discussions
Any unused outputs should not be connected to anything for non-PLL based buffers like CY2304NZ (NZDB), CY2CC910, CY2DL1510 (HPB) for example. For the non-PLL based buffers, unused outputs can be left floating.Show Less
AN69091 discusses the Edge Align feature in Cypress’s programmable clock family, CY254xx and MoBL® clocks. Today’s technology products operate at GHz frequency; therefore need complex clock-tree architecture. This need requires clock skew in the system. To address such applications, Cypress has added the Edge Align feature in CY254xx and MoBL clock family.Show Less
FleXO™ is a family of low phase noise clock generators and oscillators, consisting of both fixed frequency devices and programmable devices and with phase jitter as low as 1pS.
Have a look at the video and Application note which talks about configuring and programming of Flexo Devices.
High Performance Buffers CY2DP1502, CY2DP1504 and CY2DP1510 now support HCSL as well at the inputs. Accordingly, Cypress updated respective datasheets supporting differential input clock types to include HCSL in Features, Pin Definitions, and DC specs table sections of the datasheet.Show Less
Jitter in programmable clocks is dependent upon the configuration for your application that is determined by the frequencies selected for the outputs with respect to the reference.
A higher VCO frequency will always provide you better jitter performance that should be kept in mind always when we configure our programmable clocks. Lower frequencies generally have higher long term jitter because there is a larger chance of variation with the longer period lengths. A 1us period for a 1MHz signal with 1% of jitter can vary up to 10ns, a 10ns period for a 100MHz signal with 1% of jitter can vary up to 100ps.
With a lower frequency, if your VCO is running slower, it increases jitter, or if you are using a larger divider value, it also increases the jitter. The larger divider value can increase jitter because you have that much more logic and circuitry to go through, and each gate can add a little more variation which will accumulate and show up in the final output frequency.
The typical peak-peak period jitter value totally depends on the configuration of the device, number of outputs in use, output loading. Same frequency on all outputs and equal loading will have smaller jitter numbers. Jitter can be lowered by using the least number of outputs. Another parameter is the Q value. Using smaller Q values will also help decrease the peak-peak jitter. Different frequency combinations will yield different P and Q values, and you generally want the lowest P and Q values possible.
AVCMOS output are useful in Telecom applications where hot swapping is involved. When a card is pulled hot the device senses the load difference in multiple loads that are driven across the backplane and responds in real time.
Another use is in some devices that change load when they are active to power down. These are mainly large ASICs where drawing (sinking) some current to almost isolation can cause other ICs issues if they are sharing the same clock line.
Device Example: CY2CC810OXIShow Less
Negative R is gain that an active device provides in an oscillator circuit to overcome losses and sustain oscillation. Major component of the circuit loss is the resistance of the quartz crystal. Crystal Manufacturers specify this resistance in their crystal data sheets. Dominant Failure Mode for an Oscillator Circuit with Low Negative R or High Crystal Resistance is the oscillator failing to start when power is applied to the circuit. Negative R is an important concept in designing Oscillators. Definition of Terminology and Test Methodology is crucial for successful communication between customers and vendors. Terms should be clearly defined as misstated Jargon can cause catastrophic production and field failures.
To know how much negative R do we need? Refer to Cypress white paper- Crystal Oscillator Design and Negative Resistance by Anthony M. Scalpi available at:Show Less
One of the main failure modes for any clock is startup! Crystal specifications must be taken into consideration during oscillator circuit design. Lower cost crystals put more strain on oscillator circuit designers to provide robust startup conditions while not sacrificing reliability or other potential failure modes. Dominant Failure Mode for an Oscillator Circuit with Low Negative R or High Crystal Resistance is the oscillator failing to start when power is applied to the circuit.Show Less
When the resonant network is excited by a high gain amplifier, harmonic modes of electromechanical excitation exist. It is desirable to suppress these harmonic modes because they may not be located at perfect multiples of the fundamental mode, resulting in distortion of clock periods. Also, and perhaps more importantly, when a customer wishes to "pull" a crystal frequency, the existence of a harmonic at a frequency imperfectly aligned with an integer multiple of the fundamental mode will cause a transfer of energy in their pulling curve resulting in a discontinuity of the frequency pulling characteristic, which can make it difficult to perform trimming of a clock frequency. Frequency pulling is simply adding or removing load capacitance to tune out any inaccuracy in fundamental mode frequency.
Harmonic modes are not desirable, but they do exist in unregulated oscillators. Because harmonic modes, particularly the third overtone, do exist, specifications are often required to bound the magnitude of harmonics and the tolerance on their location relative to an ideal harmonic.
The third overtone is 3 times the fundamental frequency. R3 is the equivalent ESR of the third overtone resonant system. 3 times FNOM is the electrical third overtone, and nominally the same as the mechanical third overtone, but they are not necessarily the same frequency, which is a problem which can result in discontinuities in a frequency pulling curve. It is necessary, if electrical and mechanical third overtones are different frequencies so that the separation between the electrical and mechanical third overtones is sufficient to prevent such discontinuities from resulting in a discontinuous frequency pulling curve. Both electrical and mechanical third overtones are undesirable.