Clocks Forum Discussions
I am new to this forum and cypress IC.
I want to user DMA for caputuring 80 bits data from ADC at a speed of 8MHz.
can you guide me the speed and clock frequency for DMA used and the procedure to use DMA?
In a ‘customized’ PLL, the Q, P, and the Post-Divider are mask-programmed in a ROM. They have Fixed values and fixed frequencies.
The Drawbacks of non-programmable PLL based devices are:
1. Design (i.e. frequency) changes can be costly and time-consuming.
2. Long lead times for new custom solutions.
3. Searching for a new fixed-function part.
With Cypress programmable clock chips, the Q, P, and the Post-Divider are programmable in EPROM or EEPROM. Design changes are fast, easy and flexible. Programming a new set of P, Q, and Post-Divider values allows for design changes throughout project development.
To summarize, Cypress has Programmable synthesizers, EMI Reducing clock generators, VCXO based devices and programmable crystal oscillators that have following key advantages:
• Programmable technology allows fast prototype builds
• Generates a wide range of frequencies using low cost crystals (Xtals)
• Multi-PLL devices integrates multiple Xtals/ XOs reducing cost
• VCXO option for tuning frequency
• Spread Spectrum option for reducing EMI at its source
• Low Jitter for maximizing system reliability
• Specialty Clocks for applications in Handsets, PCI, XDR Rambus
• Low Power for portable applicationsShow Less
The High Performance Buffer products are ideally suited for systems that have a large number of high-speed interface ports (e.g., Gigabit Ethernet) or a large number of components, each requiring a copy of identical clock frequencies with minimal additive phase jitter to ensure good system timing margin.
HPB is used in a variety of applications or systems with high-speed serial (SERDES) interfaces that require differential clocks such as:
Platforms: Switches and routers, Wireless base stations, Optical networking (PON, MSTP, etc.), Blade servers, Test equipment.
High-speed interfaces: Gigabit/10-Gigabit Ethernet (GbE, 10GbE), PCI-Express, FibreChannel, SONET/SDH, CPRI.
More Areas: FPGAs, Network Processors, PLDs, Framers, PHYs.Show Less
If you're using a crystal reference, then the load capacitance can be set to a value within 6 pF to 30pF range with increments of 0.375 pF. This is done by programming a 6 bit internal register. If a driven reference is used, then this register is set to provide 6pf total (12pf on each leg of the crystal) and since XTALOUT must be left floating, the input cap load in this case, is 12 pF.
The default value in CyClocksRT software where you set this is 18.19pF for a crystal selected as a reference. So you can select a crystal of your desired frequency value (within the range specified) with 18pF load and enter the frequency value (MHz) in the REF entry box provided. You need not provide external caps to match the crystal load.Show Less
Generally the VDD pin draws more current. The AVDD pin powers the core and the PLL's, while the VDD pin powers the clock outputs. It is frequency and configuration dependant for the CY22392F. When you use CyClocksRT of CyberClocks Suite, there is a Current Consumption display in the Advanced GUI section which shows the total amount of current the device will typically need. By clicking on each of output suspend box you can see how much current that particular output consumes by subtracting the total current consumption before and after selecting the suspend option.
If all PLL's are running around 400MHz the AVDD will draw around 20mA, if all PLL's are running around 200MHz the AVDD will draw around 12mA and if all PLL's are running around 100MHz the AVDD will draw around 8mA.
You can subtract the AVDD value from the total current consumption to get the VDD current.
It is recommended connecting the Shutdown/OE pin to VDD or GND to be on the safe side. However, a 5ms pulse for Shutdown pin should not be a problem. The shutdown signal should propagate in nano seconds, the PLL and outputs should be turned off in micro seconds and the oscillator should be off in milli seconds for the CY22392.Show Less
Phase Jitter is used to characterize crystal oscillators and other devices where random (Gaussian distribution) jitter dominates. To obtain optimal performance, designers attempt to minimize phase jitter for each component in the system. As phase jitter accumulates in a high-speed system, several potential problems can arise. If the reference clock suffers from excessive phase jitter, the BER for a communications link can increase, or the dynamic range of an ADC or DAC can be limited with increased SNR. By limiting the clock phase jitter as much as possible, these and other potential problems can be avoided.
Each component in a system clock tree adds phase jitter to the clock signal. When selecting distribution components, designers should attempt to use components with the lowest additive phase jitter to give themselves the most noise margin.Show Less
The noise floor of the CY2304NZ is lower than any reference source we have, so phase noise must be measured in a two-port (residual) manner, where the E5500 measures the phase noise of the difference between the input and output signals. Above 1 MHz offset, the curve increases because the delay of the two paths was not fully matched. In reality it is most likely flat.
Attached is CY2304NZ Residual Phase Noise at 80MHzShow Less
Ganging outputs together to improve output-output skew or drive larger loads is the option usually considered. No problems can be expected with ganging from a design point of view of a device. As an alternate solution, one might try to use a high-drive version of the part first instead of ganging multiple outputs together. The high-drive version will be able to drive a larger load than the standard drive part.
The High drive versions are identified with an alphabet “H” in Cypress devices. As an example, CY2305CSXC-1H is a High drive version of its standard drive counterpart CY2305CSXC-1.Show Less
When the reference clocks phase changes, there will be a noticeable change to the output frequency as it adjusts lock to the new clock. The output will also experience high cycle-to-cycle jitter for a short time. The lock time, however, is much less than the power-on lock time.
Look at the attached document that shows how the CY22381 responds when the reference clock has a 180 degree phase change.