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Clocks Forum Discussions

Clocks Forum Discussions

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Anonymous
Clocks
Hello all,    I am new to this forum and cypress IC.    I want to user DMA for caputuring 80 bits data from ADC at a speed of 8MHz.    can you guide m... Show More
Anonymous
Clocks
In a ‘customized’ PLL, the Q, P, and the Post-Divider are mask-programmed in a ROM. They have Fixed values and fixed frequencies.    The Drawbacks of ... Show More
Anonymous
Clocks
The High Performance Buffer products are ideally suited for systems that have a large number of high-speed interface ports (e.g., Gigabit Ethernet) or... Show More
Anonymous
Clocks
If you're using a crystal reference, then the load capacitance can be set to a value within 6 pF to 30pF range with increments of 0.375 pF. This is do... Show More
Anonymous
Clocks
Generally the VDD pin draws more current. The AVDD pin powers the core and the PLL's, while the VDD pin powers the clock outputs. It is frequency and ... Show More
Anonymous
Clocks
It is recommended connecting the Shutdown/OE pin to VDD or GND to be on the safe side. However, a 5ms pulse for Shutdown pin should not be a problem. ... Show More
Anonymous
Clocks
Phase Jitter is used to characterize crystal oscillators and other devices where random (Gaussian distribution) jitter dominates. To obtain optimal pe... Show More
Anonymous
Clocks
The noise floor of the CY2304NZ is lower than any reference source we have, so phase noise must be measured in a two-port (residual) manner, where the... Show More
Anonymous
Clocks
Ganging outputs together to improve output-output skew or drive larger loads is the option usually considered. No problems can be expected with gangin... Show More
Anonymous
Clocks
When the reference clocks phase changes, there will be a noticeable change to the output frequency as it adjusts lock to the new clock. The output wil... Show More
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Clocks

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