Clocks Forum Discussions
Hello everybody,
maybe I'm only blind, but I can not figure out how to enable the VCXO,OE and PD features on the CY22801 in CyClocksRT...
I'd like to use either the CY22800 or CY22801 chip to generate a 55,5MHz clock from a 10MHz crystal + VCXO.
10MHz -> 55,5MHz on the CY22800 is not possible with InstaClock, as I can only use the predefined configurations.
Or is there a similar feature to select multiplicator/divider settings as is in CyClicksRT for the CY22801?
On the other hand, I can specify 10MHz -> 55,5MHz on the CY22801 with CyClocks, but I can not see how to enable the VCXO.
Best regards
Andreas
Hi,
I've a simple question regarding CY22150, to which I wasn't able to find a solution in datasheets, forum nor knowledge-base.
In our design, we want to minimize the period jitter of CY22150's outputs to a minimum. I've found that we have to raise VCO frequencies, but can you tell me if it is (in terms of jitter performance) better to use
- an external, low-jitter clock as a reference
- or a crystal input
- or no difference between both options?
Are there other things or settings we have to take into account to minimize the output jitter?
Thanks a lot,
bye, Harald
Show LessThe High Performance Buffer products are ideally suited for systems that have a large number of high-speed interface ports (e.g., Gigabit Ethernet) or a large number of components, each requiring a copy of identical clock frequencies with minimal additive phase jitter to ensure good system timing margin.
HPB is used in a variety of applications or systems with high-speed serial (SERDES) interfaces that require differential clocks such as:
Platforms: Switches and routers, Wireless base stations, Optical networking (PON, MSTP, etc.), Blade servers, Test equipment.
High-speed interfaces: Gigabit/10-Gigabit Ethernet (GbE, 10GbE), PCI-Express, FibreChannel, SONET/SDH, CPRI.
More Areas: FPGAs, Network Processors, PLDs, Framers, PHYs.
Show LessIf you're using a crystal reference, then the load capacitance can be set to a value within 6 pF to 30pF range with increments of 0.375 pF. This is done by programming a 6 bit internal register. If a driven reference is used, then this register is set to provide 6pf total (12pf on each leg of the crystal) and since XTALOUT must be left floating, the input cap load in this case, is 12 pF.
The default value in CyClocksRT software where you set this is 18.19pF for a crystal selected as a reference. So you can select a crystal of your desired frequency value (within the range specified) with 18pF load and enter the frequency value (MHz) in the REF entry box provided. You need not provide external caps to match the crystal load.
Show LessGenerally the VDD pin draws more current. The AVDD pin powers the core and the PLL's, while the VDD pin powers the clock outputs. It is frequency and configuration dependant for the CY22392F. When you use CyClocksRT of CyberClocks Suite, there is a Current Consumption display in the Advanced GUI section which shows the total amount of current the device will typically need. By clicking on each of output suspend box you can see how much current that particular output consumes by subtracting the total current consumption before and after selecting the suspend option.
If all PLL's are running around 400MHz the AVDD will draw around 20mA, if all PLL's are running around 200MHz the AVDD will draw around 12mA and if all PLL's are running around 100MHz the AVDD will draw around 8mA.
You can subtract the AVDD value from the total current consumption to get the VDD current.
It is recommended connecting the Shutdown/OE pin to VDD or GND to be on the safe side. However, a 5ms pulse for Shutdown pin should not be a problem. The shutdown signal should propagate in nano seconds, the PLL and outputs should be turned off in micro seconds and the oscillator should be off in milli seconds for the CY22392.
Show LessPhase Jitter is used to characterize crystal oscillators and other devices where random (Gaussian distribution) jitter dominates. To obtain optimal performance, designers attempt to minimize phase jitter for each component in the system. As phase jitter accumulates in a high-speed system, several potential problems can arise. If the reference clock suffers from excessive phase jitter, the BER for a communications link can increase, or the dynamic range of an ADC or DAC can be limited with increased SNR. By limiting the clock phase jitter as much as possible, these and other potential problems can be avoided.
Each component in a system clock tree adds phase jitter to the clock signal. When selecting distribution components, designers should attempt to use components with the lowest additive phase jitter to give themselves the most noise margin.
Show LessGanging outputs together to improve output-output skew or drive larger loads is the option usually considered. No problems can be expected with ganging from a design point of view of a device. As an alternate solution, one might try to use a high-drive version of the part first instead of ganging multiple outputs together. The high-drive version will be able to drive a larger load than the standard drive part.
The High drive versions are identified with an alphabet “H” in Cypress devices. As an example, CY2305CSXC-1H is a High drive version of its standard drive counterpart CY2305CSXC-1.
Show LessWhen the reference clocks phase changes, there will be a noticeable change to the output frequency as it adjusts lock to the new clock. The output will also experience high cycle-to-cycle jitter for a short time. The lock time, however, is much less than the power-on lock time.
Look at the attached document that shows how the CY22381 responds when the reference clock has a 180 degree phase change.
Normally additive jitter is not specified for the parts that are just fanout buffers with no PLL inside. Such a non zero delay buffer like CY2304NZ would not introduce too much additional jitter since they are just buffers (i.e. not that many transistors, simple circuit, etc.). Typical RMS Jitter that can be added to the output is approximately 10 ps for CY2304NZ and Period jitter will be less 10 ps for the CY2304NZ.
Attached are the measurements at different frequencies for a fair idea. In the document attached, kindly note that when you apply the signal from the used Agilent 8133A pulse generator (input), it has the jitter value as shown in Table 2. So Table 2 shows the jitter measured on the output of the Agilent 8133A pulse generator that is applied as the input to the CY2304NZ. The resulting output jitter is shown in Table 1 corresponding to the frequency and the type of jitter measured. So you can clearly observe that the jitter at the output is almost equal to the input. There is not much additive jitter from the buffer. So you need to have a clean source at the input.
Show Less