Clocks Forum Discussions

Regarding CY27410FLTXI(TRAY) and CY27410FLTXIT(Tape and Reel),

Please let us know TRAY specification and Tape and Reel Specification.

Its Device Package is PG-VQFN-48 (48-Pin QFN (7 × 7 × 1.00 mm) LT48D 5.6 × 5.6 E-Pad (Sawn) Package)

Best regars.

Shigeru Seike /TED

Hi all,

I'm writing an IIO driver in C for the Cypress CY22801, with communications via I2C.

However, setting the two available output clock channels generically will be difficult, as there are a lot of variables involved.

For example, I will have to calculate the values for PB, PO, Q, and DIVxN, and select the most suitable divider channel (1/2), and set the source controls for the clock outputs, for each clock output - each will affect the other one, also.

i.e. CLK_OUT_X = (2 * (pb + 4) + po) / (q + 2) / DIVxN * CLK_INPUT_FREQ

The CyClocksRT software generates all of this information automatically. Is the source code for this component of the software available, please? Or can a version of this be provided to aid our use of your products?

Many thanks,

Adam

Hi. I'm looking for the programming interface  and adapter to in house program the CY22394. It looks like the Cpress Programming kits are obsolete. Is there a ne one available, or where can I find information on how to program in house.

Thanks

Hi all,

I'm using the CY22801 clock synthesiser on a project with a Xilinx Zynq SoC and Yocto.

I'm developing a C driver and IIO wrapper for use with Linux.

However, I'm not getting a response from the IC via I2C as it seems to be pulling on the SCL line.

Pin 3 (SDAT / FS0 / VCXO / OE / PD# - serial interface data line / frequency select 0 / VCXO analog control voltage / Output Enable / Power-down) and pin 5 (CLKB / FS1 / SCLK - clock output B / frequency select 1 / serial interface clock line) are multi-function pins. How am I supposed to configure this IC for use with I2C?

Many thanks,

Adam

Hello,

I am trying to use the HCSL output with this clock generator.

The HCSL output specification in the datasheet stated the following:

Let me ask you a few questions about this.

1. There is no single-ended VOH or VOL listed here. What are the HIGH and LOW voltages at single-ended?

2. I understand that the differential voltage amplitude is 300mV (150mV-(-150mV)). Is this correct?

3. If my understanding in 2. is correct, does this voltage meet the HCSL specification?

(For example, the HCSL input specification for CY2DP1502 specifies a differential voltage of 400mV at minimum.)

Please provide an answer.

Regards,

Shimamura

Hi all,

I'm using the CY22801 clock synthesiser on a project with a Xilinx Zynq SoC and Yocto.

I can't find an existing IIO driver in the latest release of the Linux Kernel:

https://elixir.bootlin.com/linux/latest/source/drivers/iio/frequency

Is there a suitable IIO driver that I can use, please?

Failing that, is there a C driver library available that I could integrate into IIO?

Many thanks,

Adam

Hello.

Can I use this crystal for CY27410 ?

P/N: ECS-250-10-36B-CTN-TR

* ECS Inc., ECX-2236B series ( https://ecsxtal.com/ecx-2236b )
* Frequency: 25MHz
* Load Capacitance: 10pF(Specify in P/N)

Is there any replacement (either drop-in or closest) available for the part “CY7B994V-2BBI” or “CY7B994V-2BBIT”