Clocks Forum Discussions

Usually the Propagation delay, Duty Cycle, Rise and fall time values increase with increase in temperature when you go beyond the temperature grade rating for a Commercial and Industrial grade device. At higher temperatures your transistors will switch slower and your jitter will go up. If you increase your drive strength it may help to reduce jitter since you will have slightly faster edges.     

Generally the device is not characterized beyond the Industrial temperature range for an Industrial grade device and therefore the specifications like jitter or duty cycle cannot be guaranteed when the temperature range is exceeded. There are chances that the device may run in locking and reliability issues when the temperature range is exceeded and especially when you are working at the higher maximum frequencies. Usually the maximum frequency range is decreased for Industrial temperature grade as compared to commercial temperature grade that can be seen in the respective datasheet.     

Currently Cypress does not have much buffer devices in the lower MHz range or KHz range. There is CY2302 amongst zero delay buffers that can go down to 5MHz.     

Most of the zero delay buffers have a minimum input frequency of 10MHz. So operation with input reference below 10MHz minimum of the device cannot be guaranteed. If a PLL operates near the point of instability, the PLL lock time can become excessive.     

10 Mhz is a guard band of the minimum frequency. When this frequency is reached, the zero delay buffers usually will go into power down mode as it would when there is no input. There is no guarantee on any other specifications likes duty cycle, jitter, lock times etc. when the input frequency specification range is violated at the lower end.     

Even if there is no ripple at the supply source, you will see ripple at the Vdd pin of a Buffer when its outputs are switching. The switching outputs create large di/dt which causes Vdd and Vss noise both inside the chip and externally. That is why the external decoupling is so important, because only local capacitors are capable of servicing those large current transients. Also, inductance on Vss and Vdd must be minimized. When a ferrite bead is added to the Vdd path, it increases the Vdd path inductance. This is good for EMI, but it makes it that much more important that very good decoupling be provided between the ferrite and the chip.     

If still some incorrect oscillation is happening, it is likely that the poor VDD layout is playing a major roll in the problem. The VDD trace to the nearest capacitor should not be very narrow and should not be long with a Via. It’s always recommended that decoupling capacitors be placed as close as possible to the VDD pin, and that it is connect to the pin with a wide trace. So most of the VDD noise comes from the device itself, due to the multiple outputs switching, which makes good decoupling very important.     

Check for more details the following chapters of Perfect Timing II book available at: http://www.cypress.com/?rID=98     

Chapter 5 – Power Supply Filtering     

Chapter 6 – PCB Layout Considerations     

Chapter 8 – Bypass Capacitors

Tips to minimize output-output skew are as follows:

1. Keep same length transmission lines at output.

2. Allow only one frequency output simultaneously.

3. Use same Vdd on all output buffers.

4. Terminate outputs in same way; use sufficient bypass capacitors.

5. For devices in parallel, feed inputs same ref clock in most symmetrical way possible.

6. Route outputs in most symmetrical way possible.

Making a choice to go for ZDB (Zero Delay Buffer) or NZDB (Non-Zero Delay Buffer) is fairly dependent on your application requirements.

With ZDB, we have a PLL inside that gives zero delay between input and output. This filters jitter present at the reference and has less jitter at the output in ps (Jitter can be minimal but never zero).

With NZDB, there is no PLL inside; it is just a Fan-Out buffer. This is not going to filter any jitter at the input and has a propagation delay.

So while making a choice, between in a ZDB and NZDB,

You select a ZDB if your source has a bad jitter that needs filtering and you require a Zero Delay between input and Output. You will also get variants with divider options to have frequency multiplications and divisions and also can adjust skew with ZDBs.

You select a NZDB, if you have a very clean source and need just fanout of the source with less additive jitter. However, your application should be fine with the propagation delay, the NZDB will have. You will have different options to match different signaling standards here.

AVCMOS name/design came in from one of the companies Cypress acquired, IMI. It is another name for variable output impedance (VOI), or sometimes called variable slew rate (VSR). It is a type of output buffer that has a strong drive current from the beginning of a switch (ie. rise or fall time) to about the mid-point of the switch. At about mid-point, some of the legs of the transistors shut off so that the drive current is reduced, and the resulting transition from mid-point of the switch to the final settling value is smooth (i.e. little overshoot/undershoot). This way, higher frequencies can be achieved without as much overshoot/undershoot. It's called "variable impedance" because the impedance changed depending on whether you're looking at the start of the rise/fall time or the end. Actually, "variable slew rate" is perhaps a more accurate description.     

Check the KnowledgeBase Article Titled: AVCMOS Outputs of CY2CC810 Explained at: http://www.cypress.com/?id=4&rID=39987

The output impedance of Cypress Zero Delay Buffers is between 20-30 ohm, unless otherwise specified in the datasheets. So its recommended to use a 20-30 ohm series resistor to match a 50 ohm transmission line. Since the output impedance for the ZDBs is between 20-30 ohm, it is recommended to start with (X-28) Ohms series termination placed as close as possible to each output pin (where X is the transmission line impedance you connect to), thus assuming a 28 Ohms output impedance initially. So if you connect the output to 50 Ohms, then 50-28=22 Ohms series termination will be required for impedance matching.

Tracking skew can be defined as the deviation of the output of the PLL from its input.

We can expect the feedback signal to be stable as any variations there itself can cause instability with the locking and have the PLL working in Acquisition and tracking mode which are the two states of a PLL: phase-locked or acquiring lock. Any larger change to the frequency and phase to the Reference or Feedback is going to make the clock lose its lock and relock to the new frequency and phase. Cypress usually does not define and measure the tracking skew for the devices and provide as a value. It should be noted that PLLs are normally capable of tracking long-term jitter. PLLs, by design, are incapable of tracking cycle-to-cycle jitter, because the PLL response time is typically slow. When the modulation occurs at a rate and level that is too difficult for a PLL to track, the PLL may give a “best-effort” tracking which is referred to as tracking skew.     

Tracking is synonymous with the locked condition and simply describes the extent to which the loop can follow variations in the input clock frequency. PLLs operate on the phase of signals and therefore are susceptible to changes in the clock edges on the inputs. The transient response of a PLL is generally a very complex, non-linear process. In general terms, the PLL will follow the presence of a slowly occurring signal at the input and does not react to rapidly occurring transitions (frequencies outside of the PLL’s loop bandwidth).     

So with the Tracking skew, cascaded PLLs can have an adverse effect on the amount of skew exhibited. Modulations and excessive input noise that are sometimes created by jitter peaking, can lead a phase-locked loop into a condition of instability that results in less than optimal output conditions.

The jitter transfer characteristic is that of second order low-pass filter with the -3dB point at approximately 1MHz-3MHz depending on its internal configuration (also called close loop bandwidth). This means that if the jitter frequency is less than loop bandwidth, it will pass through the PLL and appear on all outputs.

Jitter transfer characteristics of clock buffers actually peaks at 1MHz where the jitter increases and then rolls down with 20-dB/decade attenuation.