Clocks Forum Discussions

Jitter in programmable clocks is dependent upon the configuration for your application that is determined by the frequencies selected for the outputs with respect to the reference.     

A higher VCO frequency will always provide you better jitter performance that should be kept in mind always when we configure our programmable clocks. Lower frequencies generally have higher long term jitter because there is a larger chance of variation with the longer period lengths. A 1us period for a 1MHz signal with 1% of jitter can vary up to 10ns, a 10ns period for a 100MHz signal with 1% of jitter can vary up to 100ps.

With a lower frequency, if your VCO is running slower, it increases jitter, or if you are using a larger divider value, it also increases the jitter. The larger divider value can increase jitter because you have that much more logic and circuitry to go through, and each gate can add a little more variation which will accumulate and show up in the final output frequency.

The typical peak-peak period jitter value totally depends on the configuration of the device, number of outputs in use, output loading. Same frequency on all outputs and equal loading will have smaller jitter numbers. Jitter can be lowered by using the least number of outputs. Another parameter is the Q value. Using smaller Q values will also help decrease the peak-peak jitter. Different frequency combinations will yield different P and Q values, and you generally want the lowest P and Q values possible.

AVCMOS output are useful in Telecom applications where hot swapping is involved. When a card is pulled hot the device senses the load difference in multiple loads that are driven across the backplane and responds in real time.     

Another use is in some devices that change load when they are active to power down. These are mainly large ASICs where drawing (sinking) some current to almost isolation can cause other ICs issues if they are sharing the same clock line.     

Device Example: CY2CC810OXI     

Negative R is gain that an active device provides in an oscillator circuit to overcome losses and sustain oscillation. Major component of the circuit loss is the resistance of the quartz crystal. Crystal Manufacturers specify this resistance in their crystal data sheets. Dominant Failure Mode for an Oscillator Circuit with Low Negative R or High Crystal Resistance is the oscillator failing to start when power is applied to the circuit. Negative R is an important concept in designing Oscillators. Definition of Terminology and Test Methodology is crucial for successful communication between customers and vendors. Terms should be clearly defined as misstated Jargon can cause catastrophic production and field failures.

To know how much negative R do we need? Refer to Cypress white paper- Crystal Oscillator Design and Negative Resistance by Anthony M. Scalpi available at:

http://www.cypress.com/?docID=9180

One of the main failure modes for any clock is startup! Crystal specifications must be taken into consideration during oscillator circuit design. Lower cost crystals put more strain on oscillator circuit designers to provide robust startup conditions while not sacrificing reliability or other potential failure modes. Dominant Failure Mode for an Oscillator Circuit with Low Negative R or High Crystal Resistance is the oscillator failing to start when power is applied to the circuit.

When the resonant network is excited by a high gain amplifier, harmonic modes of electromechanical excitation exist. It is desirable to suppress these harmonic modes because they may not be located at perfect multiples of the fundamental mode, resulting in distortion of clock periods. Also, and perhaps more importantly, when a customer wishes to "pull" a crystal frequency, the existence of a harmonic at a frequency imperfectly aligned with an integer multiple of the fundamental mode will cause a transfer of energy in their pulling curve resulting in a discontinuity of the frequency pulling characteristic, which can make it difficult to perform trimming of a clock frequency. Frequency pulling is simply adding or removing load capacitance to tune out any inaccuracy in fundamental mode frequency.

     

Harmonic modes are not desirable, but they do exist in unregulated oscillators. Because harmonic modes, particularly the third overtone, do exist, specifications are often required to bound the magnitude of harmonics and the tolerance on their location relative to an ideal harmonic.

The third overtone is 3 times the fundamental frequency. R3 is the equivalent ESR of the third overtone resonant system. 3 times FNOM is the electrical third overtone, and nominally the same as the mechanical third overtone, but they are not necessarily the same frequency, which is a problem which can result in discontinuities in a frequency pulling curve. It is necessary, if electrical and mechanical third overtones are different frequencies so that the separation between the electrical and mechanical third overtones is sufficient to prevent such discontinuities from resulting in a discontinuous frequency pulling curve. Both electrical and mechanical third overtones are undesirable.

Here is a sample list of frequencies and applications for which FleXO can provide a cost-effective alternative to XO and SO solutions:

100.00 MHz – PCI, SATA, SAS

106.25 MHz – Fibre Channel 1, 2

122.88 MHz – Wireless

125.00 MHz – Gigabit Ethernet, PCI, Infiniband

132.8125 MHz – Fibre Channel, Wireless

153.60 MHz – Wireless

155.52 MHz – SONET

156.25 MHz – 10 Gigabit Ethernet XAUI

159.375 MHz – 10 Gigabit Fibre Channel XAUI

212.50 MHz – 4 and 8 Gigabit Fibre Channel, FCoE

311.04 MHz – SONET

312.50 MHz – 10 Gigabit Ethernet XAUI

622.80 MHz – SONET OC192

All of these frequencies are supported by FleXO and have pre-configured factory devices available for sampling or order. Typical phase jitter specifications for these frequencies and applications are all below 1 ps RMS, providing sufficient performance for most designs.

Check Whitepaper: FleXO™: Bridging the Cost/Performance Gap in the Oscillator Market at:

http://www.cypress.com/?docID=23954

The jitter transfer characteristic is that of second order low-pass filter with the -3dB point at approximately 1.5MHz. This means that if the jitter frequency is less then than loop bandwidth, it will pass through the PLL and appear on all outputs. Otherwise the filter will attenuate the jitter at the rate 20dB per decade. The cycle-to-cycle jitter of REF is really high frequency, it will be greatly attenuated. The primary causes of cycle-to-cycle jitter for the output are power supply noise on PLL's supply inputs and random thermal the mechanical noise. So there is no spec for the input REF cycle-to-cycle jitter. If it is less than then 300ps for the REF input cycle-to-cycle jitter, it will be fine. If the input clock with 2ns cycle-to-cycle jitter, the ZDBs (CY23xx) like CY2308 or CY2309 for example would not lock. If the input clock has 2ns low frequency jitter (much lower than 1.5MHz), the ZDBs will keep lock and keep the cycle-to-cycle jitter 200ps. But the output will track the input low frequency jitter. The period jitter will be close to 2ns.

There are weak pull-down for REF input and all outputs of Cypress clock buffers that can be checked in respective datasheets. One do not need to provide pull-downs, but if really needed, 5K or 10K can be fine. The lower the resistor value, the strong it will pull. In cases where the input frequency drops below about 2 MHz, the PLL powers down and the outputs are tri-stated. In this case, the outputs are pulled low by these pull down resistors to provide a known state.     

At lower temperature, transistors become faster, so edge rates would become faster.

Generally, we would expect the following parameters getting affected as temperature decreases beyond the specified operating limit:

1) Decreased frequency operating range (for reliable locking)
2) Faster edge rates
3) Higher jitter
4) Duty Cycle     

Operating a device outside of its design range is very risky. While it is possible that the only effects of operating at a reduced temperature will be shifts to some parameters such as duty cycle and edge rates, it is also possible that the device performance may degrade more seriously. It may also fail to operate reliably. For example, the PLL may not lock or may lose lock, or the spread profile in case of spread aware buffers could become much distorted.     

Usually the CY2308 is not designed as a Fail Safe device. However, the PLL of the 2308 will not lose lock as a consequence of the oscillator being pulled by a few hundred PPM. The 2308 PLL will be able to track any low frequency variations in the reference input and will filter out any high frequency variations greater than the loop bandwidth which is around 1 to 2 MHz, typically 1.5 MHz.

Cypress System Engineers have tested this glitch operation for different reference frequencies: 33MHz, 66 MHz, 100 MHz, and 133MHz. The signal at the PLL output remained for the minimum of 2.3uSec after the input signal was shut off. This free running output frequency drifted slowly but no glitch was observed in any case. The measurement was under 3.3V power supply room temperature. So accordingly, it would not lose lock with a single glitch.