Clocks Forum Discussions
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The default settings for a blank Field programmable device shipped by the factory are all bits set to 0, all outputs tristated, and the crystal oscillator circuit active unless the devices are programmed by your distributor as per your default needs that you will let him know. While using I2C for serial programming such a blank device, unused registers should be left alone. Programming them all to 0's could cause unwanted behavior depending on which register it is. The OscCap value should be set to [000000] to have the least amount of capacitance when an external driven reference is used.
Show LessIf you configure a programmable device with 0 PPM error and your reference configured has some ppm error to the input frequency, the error at the input reference comes out as the same error for the output.
Show LessMany of you may think of going beyond the datasheet maximum specification of Capacitive Loading.
Generally it is possible to drive two loads from one pin; however, it is good to be cautious.
1. With Increased loading, two loads will double the capacitance loading. Maximum loading is 15pF specified in datasheets. The total device loading becomes ~30pF, which is enough to noticeably affect the edge rate.
2. Signal integrity: With two loads, layout is important. If the two loads are very close together, then it's possible to have one trace which then branches very close to the loads. However, this is not common. More commonly it is recommended branching very close to the output of the programmable clock. Then have a series resistor for each branch, located close to the branch. The resistor values will be different than when terminating a single load. Simulations are always recommended.
3. Total loading for the chip: Double loading every output on a chip has a cumulative effect on the chip and is generally discouraged. It's good if the double load is only on a single output. It's best if the other outputs are not used. If they are used, especially for different frequencies, then the heavy loading on this output may increase jitter in the other outputs.
During power up, important events takes place where the start up registers are loaded to put the part in a start-up condition. If the power ramp is not monotonic, the startup conditions will be lost and the device may come in an unknown state and not behave as expected.
It is strictly recommended that the power ramp be applied as specified in the respective datasheets.
There are internal weak pull-down for all the outputs. You do not need to provide pull-downs, however if you would like to provide pull downs, 5K or 10K is fine. The lower the resistor value, the strong it will pull.
In cases where the input frequency drops below about 2 MHz, the PLL powers down and the outputs are tri-stated. In this case, the outputs are pulled low by these resistors to provide a known state.
Show LessAny unused outputs should not be connected to anything for non-PLL based buffers like CY2304NZ (NZDB), CY2CC910, CY2DL1510 (HPB) for example. For the non-PLL based buffers, unused outputs can be left floating.
Show LessAN69091 discusses the Edge Align feature in Cypress’s programmable clock family, CY254xx and MoBL® clocks. Today’s technology products operate at GHz frequency; therefore need complex clock-tree architecture. This need requires clock skew in the system. To address such applications, Cypress has added the Edge Align feature in CY254xx and MoBL clock family.
http://www.cypress.com/?rID=50769
Show LessFleXO™ is a family of low phase noise clock generators and oscillators, consisting of both fixed frequency devices and programmable devices and with phase jitter as low as 1pS.
Have a look at the video and Application note which talks about configuring and programming of Flexo Devices.
http://www.cypress.com/?rID=45566
Thanks
Puru
Show LessHave a look at this video and application note for Understanding of Zero Delay Buffers and its different Applications.
http://www.cypress.com/?rID=12622
Thanks
Puru
Show LessHigh Performance Buffers CY2DP1502, CY2DP1504 and CY2DP1510 now support HCSL as well at the inputs. Accordingly, Cypress updated respective datasheets supporting differential input clock types to include HCSL in Features, Pin Definitions, and DC specs table sections of the datasheet.
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