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Mitchell_shen
Clocks
有一個VCXO Phase Noise 測試問題, 當VC=1/2 VDD時, Phase Noise 測試會有spur產生 而如果避開VC=1/2VDD 就不會. 但是對於VCXO產品, 標準與客戶要求VC=1/2VDD 進行量測基本數據,那麼會有問題的? 請問Cypress 是否有建議的方案, ... Show More
AtSi_2703131
Clocks
Could somebody please advise functional or drop-in equivalents for Clock generator part CY22150 which is recommended for new design has a long life cy... Show More
Mitchell_shen
Clocks
We had measurement LVDS 1.8V 40Mhz~100Mhz  RMS phase jitter performance about 1.0~1.5ps @12K-20M.But datasheet only show fOUT = 156.25 MHz,12 kHz–20 M... Show More
yach_4370576
Clocks

This is for Commscope service/spare dept.

GrBa_3991371
Clocks
I am having a problem in production where the frequency output of the CY2291 is outside previously established tolerances.  I am trying to calculate w... Show More
IdSa_1620816
Clocks

If not, what is the drop in replacement?

ToIk_1341346
Clocks
Dose CY2308SXC-1 compatible for ROHS2? Show More
kaquc_2151576
Clocks
CY2304SXI-2
Solved
As a follow on to this closed discussion: https://community.cypress.com/message/187923We’ve tried put ferrite beads, but it made the ripples worse, th... Show More
xiaowei_li_3787
Clocks
Hi,I am using the chips of Cypress recently. In out prevenient design, we were using the Clock Distribution Buffer chip, which is CY29940AXI.But today... Show More
Mitchell_shen
Clocks

Have Cypress clock & buffer product roadmap for PCIe 4.0 application?

Thanks,

Mitchell

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Clocks

Discussion Forum regarding Clocks topics.