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dalton
Clocks
Hi All, I am using the CY26049-20 as a synchronized clock filtering circuit with  with fall back So I hope to apply a 25MHz ICLK   and obtain a  100 M... Show More
anonymous-sj
Clocks
I just programmed CY29421FLXI-ND using the clockwizard. When look at each output (single ended) on the scope, i see both clk+ and clk- in sync. Basica... Show More
anonymous-sj
Clocks
Does CY29421FLXI-ND support VCXO function? i notice it lacks VC pin. Do I need to disabled this function in clockwizard tool for CY29421FLXI-ND?     Show More
JB_O
Clocks
Hi all, What are the conditions required by Infineon in term of MOQ for having a factory configured CY2545QI ? Also, what would be the extra lead time... Show More
anonymous-sj
Clocks
I am planning to use CY29421FLXI-ND on 3.3V rail, but looks like I2C port is only spec at 2.5V max. is this correct? Can i pull up I2C signals to 3.3V... Show More
anonymous-sj
Clocks
I need help on how to generate programming file for CY29421FLXI-ND to give to the programming house. we need to set the following options: Output=156... Show More
TeMa_2997106
Clocks
I am using CY2305 with the configuration shown in the schematic below. I measured the waveform of CLK1. It has a lot of jitter. (Approximately 2ns) ... Show More
collstep
Clocks
Hi, We use CY2305SXI-1H on a design where we are receiving back for several customer defect reports during start-up at low temperature (lower than 10°... Show More
MAO
Clocks
CSD
Solved

What is the min / max value of Vref of CSDv2?

MAO
Clocks
CSD
Solved

Which clock source is actually selected when Sense Clock Source is set to "Auto" in the CSD settings?