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Clocks Forum Discussions

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For the CY22050 and CY22150, the AVDD powers the PLL, VDD powers the crystal oscillator and CLK5 and CLK6, and VDDL powers LCLK1-LCLK4. You should bring up both VDD and AVDD with a smooth monotonic ramp, but VDDL can be powered up or down at any time. Powering it down while still powering AVDD and VDD is not a problem.




During power up, important events takes place where the start up registers are loaded to put the part in a start-up condition. If the power ramp is not monotonic, the start up conditions will be lost and the device may come in an unknown state and not behave as expected. So it is recommended that the power ramp specification be applied as specified in the datasheets.

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