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Phase Jitter is used to characterize crystal oscillators and other devices where random (Gaussian distribution) jitter dominates. To obtain optimal performance, designers attempt to minimize phase jitter for each component in the system. As phase jitter accumulates in a high-speed system, several potential problems can arise. If the reference clock suffers from excessive phase jitter, the BER for a communications link can increase, or the dynamic range of an ADC or DAC can be limited with increased SNR. By limiting the clock phase jitter as much as possible, these and other potential problems can be avoided.





Each component in a system clock tree adds phase jitter to the clock signal. When selecting distribution components, designers should attempt to use components with the lowest additive phase jitter to give themselves the most noise margin.

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