Output jitter in CY2305

[TeMa_2997106]

I am using CY2305 with the configuration shown in the schematic below.

I measured the waveform of CLK1. It has a lot of jitter. (Approximately 2ns)

According to the data sheet, Cycle-to-cycle jitter is 200ps(max), but there is no Period jitter spec. Is this waveform normal? If yes, what can I do to reduce jitter?

I measured CLK1, but the waveform (jitter) is the same for the other output pins. It does not change depending on the load of the opposite device. Jitter tends to increase at high temperatures.

Thanks,
Tetsuo

[PradiptaB_11 · Accepted solution]

Hi @TeMa_2997106 ,

I am adding the link for our app note that describe the working of the Zero delay buffers and our recommended schematic for above applications. Also it will explain the termination of CLKOUT pin with respect to other [pin for lead and lag adjustment or zero delay adjustment. Kindly go through the documentation once and let us know if you have any further queries.

https://www.cypress.com/file/38066/download

Thanks,

Pradipta.

[TeMa_2997106]

Pradipta-san,

The system is the same as Figure 17 in this AN. I think there is no problem with the circuit.

Why is the phase out of phase between REF and CLK1-4? I didn't understand even after reading AN.

Thanks,
Tetsuo

[TeMa_2997106]

Is there any update information about my comment?

Thanks,
Tetsuo