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Clocks Forum Discussions

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 The typical peak-peak period jitter value is completely determined by the configuration of the device. In general, jitter can be reduced by using the least number of outputs and PLL's, or using smaller Q values. We can optimize the parameters P and Q. You can calculate the P and Q values using the Cyberclocks software, available on our website. The jitter varies with the different configurations. There are certain factors that help in minimizing jitter for a particular configuration. 


Your jitter will be reduced when you minimize the number of PLL's running on the die. The worst case jitter depends on how many outputs and PLL's are running as well as what combinations of frequencies are running on the chip.

Keeping VCO frequencies high as possible will always give you better jitter performance. The way to minimize jitter is to run the minimum number of outputs and PLL's. Also having clean multiples of the input frequency will help reduce jitter in some cases as well.

Lower frequencies generally have higher long term jitter because there is a larger chance of variation with the longer period lengths. A 1us period for a 1MHz signal with 1% of jitter can vary up to 10ns, a 10ns period for a 100MHz signal with 1% of jitter can vary up to 100ps.

So with a lower frequency, either your VCO is running slower which increases jitter, or you are using a larger divider value which can also increase the jitter. The larger divider value can increase jitter because you have that much more logic and circuitry to go through, and each gate can add a little more variation which will accumulate and show up in the final output frequency.

So again, in cases where reducing jitter is of paramount importance, it is recommended running fewer PLLs in case of multi-PLL devices.

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