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We had measurement LVDS 1.8V 40Mhz~100Mhz RMS phase jitter performance about 1.0~1.5ps @12K-20M.
But datasheet only show fOUT = 156.25 MHz,12 kHz–20 MHz offset, non-VCXO mode MAX. is 250fs(0.25ps).
Could you help check 40Mhz~100Mhz bandwidth jitter performance 1.0~1.5ps @12K-20M are resonable?
Have any test data can share?
Thanks,
Mitchell
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Programmable Clocks
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Hi Mitchell,
We can suggest you to use an appropriate combiner in the circuitry to view better Phase noise plots.
Thanks,
Pradipta.
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Hi Mitchell,
We are checking for the test data. Meanwhile can you let us know the termination settings for the LVDS which you have used and can you share your jitter plots with us.
We also have an app note for the device which gives reference termination settings(page 8). have you used a similar setting for the device. Can you also share the schematics for the clock part.
https://www.cypress.com/file/294351/download
Thanks and Regards,
Pradipta.
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Dear Pradipta.,
Customer termination same as app note as your mention.
Below are 40Mhz/50Mhz/75Mhz jitter plots for reference.
40Mhz:
50Mhz:
75Mhz:
Thanks,
Mitchell
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Hi Mitchell,
We can suggest you to use an appropriate combiner in the circuitry to view better Phase noise plots.
Thanks,
Pradipta.
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Dear Pradipta,
Could you share combiner circuit or balun board information for reference?
Thanks,
Mitchell
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Hi Mitchell,
We use the Mini-circuits Splitter ZFSCJ-2-4-S+. You can check this out as a reference.
Thanks,
Pradipta.