CY29421FLXIT LVDS VOH and VOL

[Anonymous]

Hello,

   

1) I cannot find anywhere in the datasheet the information regarding VOH and VOL for output type of LVDS standard.

   

2) Please refer to LVDS common mode and swing when working with all possible input voltages VDD=1.8V, VDD=2.5V and VDD=3.3V.

   

3) The information in the datasheet regarding the power supplies is ambiguous, there are two power supplies VDD and VDDO when actually there is no pin in the IC for separate outputs power supply VDDO and the user cannot provide different power supply for core and for output drivers.

   

4) Does the eFuse can be programmed using VDD=1.8V? The only infomation regarding this issue is "Programming voltage....2.5V+/-0.1V" in the "Absolute Maximum Rating" section. It can be programmed only by using VDD=2.5V? or 1.8V is also okay?

   

Regards,

   

Haim.

[Anonymous]

Hello Haima,

   

4) Does the eFuse can be programmed using VDD=1.8V? The only infomation regarding this issue is "Programming voltage....2.5V+/-0.1V" in the "Absolute Maximum Rating" section. It can be programmed only by using VDD=2.5V? or 1.8V is also okay?

   

A) eFuse should be programmed using VDD = 2.5V only not 1.8V.

   

Thanks,

   

Krishna.

[Anonymous]

Thanks, Krishna!

   

What about questions 1+2+3 would you please answer them too?

   

I need this information as soon as possible in order to finish my design.

   

Haim.

[AmitavaB_46 · Accepted solution]

Hi Haim,
Please find the answers of your queries here below :

   

Answer of (1) and (2): For the LVDS standard, instead of specifying the VOH and VOL values in the datasheet, we specify output-common-mode-voltage (Vcm), and the peak-to-peak voltage (Vp). In the datasheet, we specify Vcm set by the output driver is 1.2V when Vdd = 2.5V / 3.3V. Vcm is the average value, and there is a differential swing around Vcm. We define Vp in the datasheet, the upper and lower limits of which are given below :
247mV < Vp < 454mV : up to 700MHz frequency
150mV < Vp < 454mV : 700MHz to 2.1GHz

   

You can find this number under the 'Vp' spec in the Table "AC Electrical Specifications for LVPECL, LVDS, CML Outputs" in the datasheet. 

   

But when Vdd is at 1.8v, output driver cannot accurately set the Vcm to 1.2V. Hence we recommend users of the 1.8V LVDS clock to set the
common-mode externally (with AC coupling). This 1.8v termination circuit iis explained in the Section 2.2, and Figure 7 of our
Application Note (Link : http://www.cypress.com/documentation/application-notes/an210253-cy294xx-high-performance-clock-getti... ). Once Vcm is set externally, Vp for 1.8v is same as that of 2.5v/3.3v.

   

Answer of (3): Though the CY29430 device datasheet shows different supply - VDD and VDDO, the device should be used for same power domain. These two supply pins are recommended to short on the board. We would like to recommend the CY3677 EVK schematic that is available in the following link to design with CY29430 : http://www.cypress.com/documentation/development-kitsboards/cy3677-evaluation-kit

   

Answer of (4): For eFuse programming, we strictly need to set the device power-supply between 2.4V to 2.6V. User can set any Vdd=1.8/2.5/3.3V in
the sftware configuration, but "eFuse programming" of the device only happens for Vdd between 2.4V to 2.6V. After the eFuse programming
is over, user needs to power cycle the device. The eFuse programmed device when used in any application, the physical supply on the board, and the supply settings written in the device configuration - these two must match.

   

Please let us if you have any doubt on this, or you need more clarification. 

   

Regards,
Amitava