Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
NaMo_1534561
Level 5
Level 5
Distributor - Macnica (Japan)
100 replies posted 100 sign-ins 50 replies posted

Hello,

I have a question about the Cypress clock buffer (CY2308ZXI-1HT).

The Switching Characteristics parameter t5 specifies the output skew between each port of the output terminals CLKA1 to 4 and CLKB1 to 4.

t5 is,
- using internal PLL (S2 = 1, S1 = 1)
- does not use the internal PLL (S2 = 1, S1 = 0) (= Mode that outputs the REF clock signal)
In either case, is the output skew between each port specified by t5?

MPN: CY2308ZXI-1HT

Data sheet "Document Number: 38-07146 Rev. * T"
https://www.cypress.com/file/38856/download

 

Best Regards,

Naoaki Morimoto

 

0 Likes
1 Solution
PradiptaB_11
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi Morimoto-san,

The t5 parameter which the output to output skew is valid for both modes (when PLL is used and when only REF is used and PLL is bypassed). In either case the output skew between each port specified by t5.

Thanks,

Pradipta

View solution in original post

0 Likes
2 Replies
PradiptaB_11
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi Morimoto-san,

The t5 parameter which the output to output skew is valid for both modes (when PLL is used and when only REF is used and PLL is bypassed). In either case the output skew between each port specified by t5.

Thanks,

Pradipta

0 Likes
NaMo_1534561
Level 5
Level 5
Distributor - Macnica (Japan)
100 replies posted 100 sign-ins 50 replies posted

Hi Pradipta-san,

Thank you for giving answer. This query has been resolved.

Best Regards,

Naoaki Morimoto

 

0 Likes